CDP1878C View Datasheet(PDF) - Intersil
Part Name
Description
Manufacturer
CDP1878C Datasheet PDF : 13 Pages
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CDP1878C
MODE
CONTROL REGISTER
GATE CONTROL
4
Rate Generator
Selectable High or Low
X X X X X 1 0 0 Level Enables Operation
BUS 7
BUS 0
Mode 4
A repetitive clock-wide output pulse will be output, with the
time between pulses equal to the counter’s value, (trailing
edge to leading edge). This model is software started with a
write to the control register if the gate level is valid. If the
counter is written to while decrementing, the new value will
not affect the counter’s operation until the present timeout
has concluded, unless the control register is written to with
the jam-enable bit high. If the gate input (TAG or TBG) is
used to start this mode, the first cycle following the gate
going true is indeterminate.
COUNTER VALUE
CLOCK
WR CONTROL
REGISTER
3
2
1
0
3
2
1
0
3
N
3
2
1
0
3
2
1
0
3
N
GATE
TXO
INT
LOAD COUNT = 3
FIGURE 4. RATE GENERATORS (MODE 4) TIMING WAVEFORMS
MODE
CONTROL REGISTER
GATE CONTROL
5
Variable Duty Cycle
Selectable High or Low
X X X X X 1 0 1 Level Enables Operation
BUS 7
BUS 0
Mode 5
After the mode is initiated, the outputs will remain at one
level until the clock decrements the least significant byte of
the counter to N+1. The outputs will then change level and
the counter decrements the most significant byte to N+1.
The process will then repeat, resulting in a repetitive output
with a duty cycle directly controlled by the value in the
counter. The output period will be equal to LSB+MSB+2.
The interrupt output will become active after the MSB is
loaded into the counter and decrements to zero.
COUNTER VALUE
CLOCK
WR CONTROL
REGISTER
GATE
2
2
1
1
0
1
0
2
1
0
1
0
1
0
2
1
0
1
TXO
LSB
MSB
LSB
INT
LOAD COUNT LSB = 2 AND MSB = 1
FIGURE 5. VARIABLE-DUTY CYCLE (MODE 5) TIMING WAVEFORMS
NOTE: In order to avoid unwanted starts when selecting mode 3 or 4, the gate signal must be set to the opposite level that will be pro-
grammed.
4-98
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