CDP68HC68T1(1997) View Datasheet(PDF) - Intersil
Part Name
Description
Manufacturer
CDP68HC68T1 Datasheet PDF : 24 Pages
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CDP68HC68T1
Dynamic Electrical Specifications Bus Timing VDD ±10%, VSS = 0VDC, TA = 40oC to 85oC
LIMITS (ALL TYPES)
IDENT. NO
PARAMETER
VDD = 3.3V
MIN
MAX
VDD = 5V
MIN
MAX
1
Chip Enable Setup Time
2
Chip Enable After Clock Hold Time
3
Clock Width High
4
Clock Width Low
5
Data In to Clock Setup Time
7
Clock to Data Propagation Delay
8
Chip Disable to Output High Z
11
Output Rise Time
12
Output Fall Time
A
Data in After Clock Hold Time
B
Clock to Data Out Active
C
Clock Recovery Time
tEVCV
tCVEX
tWH
tWL
tDVCV
tCVDV
tEXQZ
tr
tf
tCVDX
tCVQX
tREC
200
-
100
-
250
-
125
-
400
-
200
-
400
-
200
-
200
-
100
-
-
200
-
100
-
200
-
100
-
200
-
100
-
200
-
100
200
-
100
-
-
200
-
100
200
-
200
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
16
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