AD7716BS View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
AD7716BS Datasheet PDF : 16 Pages
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AD7716
Table I. Typical Usable Dynamic Range, RMS Noise and Filter Settling Time vs. Filter Cutoff Frequency
Programmed Cutoff Output Update Usable Dynamic RMS Noise Filter Settling Time to
N Frequency (Hz)
Rate (Hz)
Range (dB)
(V)
؎0.0007% FS (ms)
0 584
1 292
2 146
3 73
4 36.5
2232
99
1116
102
558
105
279
108
140
111
21
1.35
14
2.7
10
5.4
7
10.8
5
21.6
NOTE
Usable Dynamic Range is defined as the ratio of the rms full-scale reading (sine wave input) to the rms noise of the converter.
Absolute Group
Delay (ms)
0.675
1.35
2.7
5.4
10.8
CONTROL REGISTER TIMING CHARACTERISTICS1, 2 (AVDD= DVDD = +5 V ؎ 5%; AVSS = –5 V ؎ 5%; AGND =
DGND = 0 V; fCLKIN = 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DVDD; unless otherwise noted)
Parameter
Limit at TMIN, TMAX
(B Version)
Units
Conditions/Comments
t1
1/fCLKIN
t2
77
t3
30
t4
20
t5
10
t6
20
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Period
SCLK Width
TFS Setup Time
SDATA Setup Time
SDATA Hold Time
TFS Hold Time
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figure 2.
3CLKIN Duty Cycle range is 40% to 60%.
SCLK (I)
TFS (I)
SDATA (I)
1.6mA IOL
TO
OUTPUT
PIN
CL
50pF
200µA IOH
+2.1V
Figure 1. Load Circuit for Access Time and Bus Relinquish Time
t2
t1
t2
t3
t4
t5
DB0
(DB8)
DB1
(DB9)
DB2
(DB10)
DB3
(DB11)
DB4
(DB12)
DB5
(DB13)
t6
DB6
(DB14)
DB7
(DB15)
Figure 2. Control Register Timing Diagram
REV. A
–3–
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