AD7731(1997) View Datasheet(PDF) - Analog Devices

Part Name

Description

Manufacturer

AD7731
(Rev.:1997)

Low Noise, High Throughput 24-Bit Sigma-Delta ADC

Analog Devices 

AD7731

INPUT CHOPPING

THE ANALOG INPUT TO THE PART

CAN BE CHOPPED. IN CHOPPING MODE,

THE INPUT IS CHOPPEDAND THE OUTPUT OF

THE FIRST STAGE FILTER IS CHOPPED

REMOVING ERRORS IN THAT PATH.

THE DEFAULT CONDITION IS

CHOPPING DISABLED

SEE PAGE 25

SINC3 FILTER

THE FIRST STAGE OF THE DIGITAL

FILTERING ON THE PART IS THE

SINC3 FILTER. THE OUTPUT UPDATE

RATE AND BANDWIDTH OF THIS

FILTER CAN BE PROGRAMMED. IN

SKIP MODE, THE SINC3 FILTER IS

THE ONLY FILTERING PERFORMED

ON THE P3T.

SEE PAGE 25

SKIP MODE

IN SKIP MODE, THERE IS NO

SECOND STAGE OF FILTERING ON

THE PART. THE SINC3 FILTER IS

THE ONLY FILTERING PERFORMED

ON THE PART. THIS IS THE

SECOND STAGE FILTER

SEE PAGE 25

ANALOG

INPUT

CHOP

BUFFER

PGA &

SIGMA-DELTA

MODULATOR

SINC3

FILTER

CHOP

22-TAP

FIR FILTER

SKIP

FASTSTEP™

FILTER

22-TAP FIR FILTER

WITH SKIP DISABLED, THE NORMAL

OPERATING MODE OF THE SECOND STAGE

OF THE DIGITAL FILTERING ON THE PART IS

A FIXED 22-TAP FIR FILTER. IN SKIP MODE,

THIS FIR FILTER IS BYPASSED. WHEN

FASTSTEP™ MODE IS ENABLED AND A

STEP INPUT IS DETECTED, THE SECOND

STAGE FILTERING IS PERFORMED BY THE

FAST STEP FILTER UNTIL THE OUTPUT OF

THIS FILTER HAS FULLY SETTLED

SEE PAGE 26

OUTPUT

SCALING

DIGITAL

OUTPUT

BUFFER

THE INPUT SIGNAL IS BUFFERED

ON-CHIP BEFORE BEING APPLIED

TO THE SAMPLING CAPACITOR OF

THE SIGMA DELTA MODULATOR.

THIS ISOLATES THE SAMPLING

CAPACITOR CHARGING CURRENTS

FROM THE ANALOG INPUT PINS

SEE PAGE 23

PGA & SIGMA-DELTA

MODULATOR

THE PROGRAMMABLE GAIN

CAPABILITY OF THE PART IS

INCORPORATED AROUND THE

SIGMA DELTA MODULATOR.THE

MODULATOR PROVIDES A HIGH-

FREQUENCY 1-BIT DATA STREAM

TO THE DIGITAL FILTER.

SEE PAGE 24

OUTPUT CHOPPING

THE OUTPUT OF THE FIRST STAGE

OF FILTERING ON THE PART CAN

BE CHOPPED. THE DEFAULT

CONDITION IS CHOPPING

DISABLED

SEE PAGE 25

FASTSTEP™ FILTER

YY

WHEN FASTSTEP™ MODE IS

ENABLED AND A STEP CHANGE ON

THE INPUT HAS BEEN DETECTED,

THE SECOND STAGE FILTERING IS

PERFORMED BY THE FASTSTEP™

FILTER UNTIL THE FIR FILTER HAS

FULLY SETTLED.

SEE PAGE 28

Figure 3. Signal Processing Chain

OUTPUT SCALING

THE OUTPUT WORD FROM THE

DIGITAL FILTER IS SCALED BY THE

CALIBRATION COEFFICIENTS

BEFORE BEING PROVIDED AS THE

CONVERSION RESULT

SEE PAGE 29

PIN CONFIGURATION

SCLK 1

24 DGND

MCLK IN 2

23 DVDD

MCLK OUT 3

22 DIN

POL 4

21 DOUT

SYNC 5

20 RDY

RESET 6 AD7731 19 CS

TOP VIEW

NC 7 (Not to Scale) 18 STANDBY

AGND 8

17 AIN6

AVDD 9

AIN1 10

16 AIN5

15 REF IN(–)

AIN2 11

14 REF IN(+)

AIN3/D1 12

13 AIN4/D0

NC = NO CONNECT

Pin Pin

No. Mnemonic

1

SCLK

2

MCLK IN

PIN FUNCTION DESCRIPTIONS

Function

Serial Clock. Schmitt-Triggered Logic Input. An external serial clock is applied to this input to transfer

serial data to or from the AD7731. This serial clock can be a continuous clock with all data transmitted in a

continuous train of pulses. Alternatively, it can be a noncontinuous clock with the information being trans-

mitted to or from the AD7731 in smaller batches of data.

Master Clock signal for the device. This can be provided in the form of a crystal/resonator or external clock.

A crystal/resonator can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN

pin can be driven with a CMOS-compatible clock and MCLK OUT left unconnected. The part is specified

with a clock input frequency of 4.9152 MHz.

REV. 0

–7–

Share Link: