CXL5506M View Datasheet(PDF) - Sony Semiconductor

Part Name

Description

Manufacturer

CXL5506M

CMOS-CCD 1H Delay Line for PAL

Sony Semiconductor 

CXL5506M/P

Pin Description

Pin No. Symbol

1 IN

2 ∗ VG2

3 OUT

4 VSS

5 CLK

6 VG1

7 VDD

8 AB

I/O

Description

I

Signal input

I

Gate bias 2 DC input

O

Signal output

—

GND

I

Clock input

O

Gate bias 1 DC output

—

Power supply (5V)

O

Auto-bias DC output

Impedance

> 10kΩ at no clamp

40 to 500Ω

> 10kΩ

600 to 200kΩ

∗ Description of Pin 2 (VG2)

Control of input signal clamp condition

0V ........ Sync tip clamp condition

5V ........ Center bias condition

Center biased to approx. 2.1V by means of the IC internal resistance (approx. 10kΩ).

In this mode, the input signal is limited to APL 50% and the maximum input signal amplitude is

200mVp-p.

Input waveform

Output waveform

Clamp

level

–2–

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