TX4939 View Datasheet(PDF) - Toshiba
Part Name
Description
Manufacturer
TX4939 Datasheet PDF : 756 Pages
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Index
Toshiba RISC Processor
TX4939
15.7. Memory Access............................................................................................................................................... 15-10
15.7.1. Address Mapping ..................................................................................................................................... 15-10
15.7.2. Wrapper Register ..................................................................................................................................... 15-12
15.8. DDR SDRAM Controller.................................................................................................................................. 15-15
15.8.1. Initialization protocol................................................................................................................................. 15-15
15.8.2. Supported DDR SDRAM Configurations.................................................................................................. 15-16
15.8.3. Delay Line Tuning .................................................................................................................................... 15-16
15.9. Register Map................................................................................................................................................... 15-18
15.10. Registers....................................................................................................................................................... 15-19
15.11. Read Data Capture ....................................................................................................................................... 15-30
15.12. Write Data Timing.......................................................................................................................................... 15-31
15.13. DDR Controller Address Mapping ................................................................................................................. 15-33
15.14. DDR Controller Interrupt ............................................................................................................................... 15-34
CHAPTER 16. PCI CONTROLLER............................................................................................................................... 16-1
16.1. Features............................................................................................................................................................ 16-1
16.1.1. Overall........................................................................................................................................................ 16-1
16.1.2. Initiator Function ........................................................................................................................................ 16-1
16.1.3. Target Function .......................................................................................................................................... 16-1
16.1.4. PCI Arbiter.................................................................................................................................................. 16-2
16.1.5. PDMAC (PCI DMA Controller) ................................................................................................................... 16-2
16.1.6. Miscellaneous ............................................................................................................................................ 16-2
16.2. Block Diagram................................................................................................................................................... 16-3
16.3. Detailed Explanation ......................................................................................................................................... 16-4
16.3.1. Terminology Explanation ............................................................................................................................ 16-4
16.3.2. Satellite Mode ............................................................................................................................................ 16-5
16.3.3. PCI Boot..................................................................................................................................................... 16-5
16.3.4. Sample PCI Adapter Configuration ............................................................................................................ 16-6
16.3.5. On-chip Register ........................................................................................................................................ 16-7
16.3.6. Supported PCI Bus Commands ................................................................................................................. 16-8
16.3.7. Initiator Access (G-Bus → PCI Bus Address Conversion)........................................................................ 16-10
16.3.8. Target Access (PCI Bus → G-Bus Address Conversion) ......................................................................... 16-12
16.3.9. Post Write Function.................................................................................................................................. 16-14
16.3.10. Endian Switching Function..................................................................................................................... 16-14
16.3.11. 66 MHz Operation Mode ........................................................................................................................ 16-15
16.3.12. Power Management ............................................................................................................................... 16-15
16.3.13. PDMAC (PCI DMA Controller) ............................................................................................................... 16-17
16.3.14. Error Detection, Interrupt Reporting ....................................................................................................... 16-20
16.3.15. PCI Bus Arbiter ...................................................................................................................................... 16-21
16.3.16. Set Configuration Space ........................................................................................................................ 16-24
16.3.17. PCI Clock ............................................................................................................................................... 16-24
16.4. PCI Controller Control Register....................................................................................................................... 16-25
16.4.1. ID Register (PCIID) .................................................................................................................................. 16-27
16.4.2. PCI Status, Command Register (PCISTATUS) ........................................................................................ 16-28
16.4.3. Class Code, Revision ID Register (PCICCREV) ...................................................................................... 16-30
16.4.4. PCI Configuration 1 Register (PCICFG1) 0xD00C.............................................................................. 16-31
16.4.5. P2G Memory Space (m) PCI Lower Base Address Register ................................................................... 16-32
16.4.6. P2G Memory Space (m) Configuration Register ...................................................................................... 16-33
16.4.7. P2G Memory Space 0 PCI Upper Base Address Register (P2GM0PUBASE)......................................... 16-34
16.4.8. P2G Memory Space 1 PCI Upper Base Address Register (P2GM1PUBASE)......................................... 16-34
16.4.9. P2G I/O Space PCI Base Address Register (P2GIOPBASE) .................................................................. 16-34
16.4.10. Subsystem ID Register (PCISID) ........................................................................................................... 16-35
16.4.11. Capabilities Pointer Register (PCICAPPTR) .......................................................................................... 16-35
16.4.12. PCI Configuration 2 Register (PCICFG2)............................................................................................... 16-36
16.4.13. G2P Timeout Count Register (G2PTOCNT)........................................................................................... 16-37
16.4.14. G2P Status Register (G2PSTATUS)....................................................................................................... 16-37
16.4.15. G2P Interrupt Mask Register (G2PMASK) ............................................................................................. 16-38
16.4.16. Satellite Mode PCI Status Register (PCISSTATUS)............................................................................... 16-39
16.4.17. PCI Status Interrupt Mask Register (PCIMASK) .................................................................................... 16-40
16.4.18. P2G Configuration Register (P2GCFG) ................................................................................................. 16-41
16.4.19. P2G Status Register (P2GSTATUS) ...................................................................................................... 16-42
16.4.20. P2G Interrupt Mask Register (P2GMASK) ............................................................................................. 16-43
16.4.21. P2G Current Command Register (P2GCCMD) ...................................................................................... 16-43
16.4.22. PCI Bus Arbiter Request Port Register .................................................................................................. 16-44
16.4.23. PCI Bus Arbiter Configuration Register (PBACFG)................................................................................ 16-46
16.4.24. PCI Bus Arbiter Status Register (PBASTATUS) ..................................................................................... 16-47
Rev. 3.3 May 18, 2007
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