TX4939 View Datasheet(PDF) - Toshiba

Part Name

Description

Manufacturer

TX4939

64-Bit TX System RISC

Toshiba 

Index

Toshiba RISC Processor

TX4939

List of Contents

LIST OF CONTENTS .......................................................................................................................................................... I

LIST OF FIGURES ........................................................................................................................................................... XII

LIST OF TABLES ............................................................................................................................................................XIX

CHAPTER 1. FEATURES................................................................................................................................................ 1-1

1.1. Abstract ................................................................................................................................................................. 1-1

1.2. Implemented Features .......................................................................................................................................... 1-1

1.3. System Block Diagram.......................................................................................................................................... 1-2

1.4. Example of Reference System.............................................................................................................................. 1-3

1.4.1. Two ATA100 for DVD Recorder ...................................................................................................................... 1-3

1.4.2. One ATA100 and Two Ethernet ...................................................................................................................... 1-4

CHAPTER 2. INTERNAL BLOCK DIAGRAM................................................................................................................. 2-1

2.1. TX4939 System Block Diagram ............................................................................................................................ 2-1

2.2. TX49/H4 Core Features ........................................................................................................................................ 2-2

2.3. Power Management Feature................................................................................................................................. 2-3

2.3.1. Strategy for Power Management.................................................................................................................... 2-3

2.3.2. Power Management for Internal Controller .................................................................................................... 2-3

2.3.3. Battery Back-Up Real Time Clock.................................................................................................................. 2-3

2.4. TX4939 Peripheral Function Features .................................................................................................................. 2-4

CHAPTER 3. PIN ASSIGNMENT AND FUNCTION ........................................................................................................ 3-1

3.1. Pin Assign Table.................................................................................................................................................... 3-1

3.2. Pin Alignment (Top View) ...................................................................................................................................... 3-4

3.3. Pin Function .......................................................................................................................................................... 3-5

3.3.1. System Clock and RESET Signals................................................................................................................. 3-5

3.3.2. DDR SDRAM Interface Signals...................................................................................................................... 3-5

3.3.3. VIDEO Port Interface Signal .......................................................................................................................... 3-6

3.3.4. ATA100 Channel 0 Interface .......................................................................................................................... 3-6

3.3.5. ATA100 Channel 1 Interface .......................................................................................................................... 3-6

3.3.6. External Bus Interface Signals ....................................................................................................................... 3-7

3.3.7. ISA Interface Signals...................................................................................................................................... 3-7

3.3.8. Default GPIO.................................................................................................................................................. 3-8

3.3.9. PCI Interface Signals ..................................................................................................................................... 3-8

3.3.10. Ethernet MAC Interface (RMII)..................................................................................................................... 3-9

3.3.11. AC-Link Interface.......................................................................................................................................... 3-9

3.3.12. I2S Interface 2-channel mode ...................................................................................................................... 3-9

3.3.13. I2S Interface 5.1 channel mode ................................................................................................................. 3-10

3.3.14. I2C Interface .............................................................................................................................................. 3-10

3.3.15. SPI Interface .............................................................................................................................................. 3-10

3.3.16. RTC Interface............................................................................................................................................. 3-10

3.3.17. SIO Interface...............................................................................................................................................3-11

3.3.18. Timer Interface ............................................................................................................................................3-11

3.3.19. Interrupt Signals ..........................................................................................................................................3-11

3.3.20. PLL Power and Ground...............................................................................................................................3-11

3.3.21. TEST and EJTAG Debugging Interface...................................................................................................... 3-12

3.4. Pin Multiplexing................................................................................................................................................... 3-13

3.4.1. Pin Multiplex for GPIO (Miscellaneous)........................................................................................................ 3-13

3.4.2. Pin Multiplexing for ACLINK and I2S............................................................................................................ 3-13

3.4.3. Pin Multiplex for ATA100-0 (Channel 0) ....................................................................................................... 3-14

3.4.4. Pin Multiplex for ATA100-1 (Channel 1) ....................................................................................................... 3-15

3.4.5. Pin Multiplex for Video port .......................................................................................................................... 3-16

3.4.6. Pin Multiplexing for ISA ................................................................................................................................ 3-17

3.4.7. Pin Multiplexing for PCICLK [4:1] ................................................................................................................. 3-17

CHAPTER 4. BOOT CONFIGURATION ......................................................................................................................... 4-1

4.1. Boot Configuration ................................................................................................................................................ 4-1

4.2. Boot Configuration Detail ...................................................................................................................................... 4-2

CHAPTER 5. CLOCK GENERATORS ............................................................................................................................ 5-1

Rev. 3.3 May 18, 2007

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