TX4939 View Datasheet(PDF) - Toshiba
Part Name
Description
Manufacturer
TX4939 Datasheet PDF : 756 Pages
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Index
Toshiba RISC Processor
TX4939
5.1. Overview ............................................................................................................................................................... 5-1
5.2. Master Clock Generator ........................................................................................................................................ 5-2
5.3. Audio Clock Generator .......................................................................................................................................... 5-3
5.3.1. Features......................................................................................................................................................... 5-3
5.3.2. Source Clock Generation ............................................................................................................................... 5-4
5.3.3. Frequency Error in the Generation of Source Clock out of 20 MHz ............................................................... 5-5
5.3.4. Restriction of Audio Clock for Over Sampling ................................................................................................ 5-7
5.3.5. Audio Clock Control Register ......................................................................................................................... 5-9
5.3.6. MCLKOSC Register ....................................................................................................................................... 5-9
5.3.7. MCLKCTL Register .......................................................................................................................................5-11
5.4. Second Baud rate Generator .............................................................................................................................. 5-12
5.5. SSCG (Spread Spectrum Clock Generator) ........................................................................................................ 5-13
5.5.1. SSCG UNIT ................................................................................................................................................. 5-13
5.5.2. Modulation Profile ........................................................................................................................................ 5-13
5.6. De-Skew Circuit .................................................................................................................................................. 5-14
5.6.1. Theory of Operation ..................................................................................................................................... 5-14
5.6.2. DDR Clock De-Skew.................................................................................................................................... 5-14
5.6.3. PCI Clock De-Skew...................................................................................................................................... 5-15
CHAPTER 6. ADDRESS MAPPING................................................................................................................................ 6-1
6.1. TX49 CPU Address Space .................................................................................................................................... 6-1
6.2. Physical Address Map Overview........................................................................................................................... 6-2
6.3. DDR SDRAM Mapping.......................................................................................................................................... 6-3
6.3.1. Fundamentals ................................................................................................................................................ 6-3
6.3.2. Control Registers ........................................................................................................................................... 6-3
6.3.3. DDR Mapping Window Control (DRWINEN) 0x8200 ................................................................................ 6-4
6.3.4. DDR Mapping Window #n (n=0, 1, 2, 3) DRWIN00 0x8208 DRWIN01 0x8210
DRWIN02 0x8218 DRWIN03 0x8220 ................................... 6-5
6.4. PCI Address Space Mapping ................................................................................................................................ 6-7
6.4.1. P2G Memory Space (n) PCI Lower Base Address Register (n=0,1,2) ........................................................... 6-7
6.5. Register Map Convention...................................................................................................................................... 6-9
6.5.1. Addressing ..................................................................................................................................................... 6-9
6.5.2. Endianness and Register size........................................................................................................................ 6-9
6.6. Register Map....................................................................................................................................................... 6-10
6.6.1. Registers for ATA0 ........................................................................................................................................6-11
6.6.2. Registers for ATA1 ....................................................................................................................................... 6-12
6.6.3. Registers for NAND Controller (NDFMC)..................................................................................................... 6-12
6.6.4. Registers for SRAM Controller (SRAMC)..................................................................................................... 6-13
6.6.5. Registers for Crypt Engine Controller........................................................................................................... 6-13
6.6.6. Registers for PCI Controller for ETHERC (PCIC1) ...................................................................................... 6-14
6.6.7. Registers for DDR SDRAM Controller (DDRC) ............................................................................................ 6-16
6.6.8. Registers for External Bus Controller (EBUSC) ........................................................................................... 6-17
6.6.9. Registers for Video Port Controller (VPC) .................................................................................................... 6-17
6.6.10. Registers for DMA Controller (DMAC0)...................................................................................................... 6-18
6.6.11. Registers for DMA Controller (DMAC1)...................................................................................................... 6-19
6.6.12. Registers for PCI Controller (PCIC) ........................................................................................................... 6-20
6.6.13. Registers for GBUS to PCI Interface.......................................................................................................... 6-21
6.6.14. Registers for Chip Configuration ................................................................................................................ 6-22
6.6.15. Registers for Timer(s) ................................................................................................................................ 6-23
6.6.16. Registers for Serial I/O............................................................................................................................... 6-24
6.6.17. Registers for Interrupt Controller (IRC) ...................................................................................................... 6-25
6.6.18. Registers for AC Link ................................................................................................................................. 6-26
6.6.19. Registers for Serial Peripheral Interface (SPI) ........................................................................................... 6-26
6.6.20. Registers for I2C Controller........................................................................................................................ 6-27
6.6.21. Registers for I2S Controller........................................................................................................................ 6-27
6.6.22. Registers for RTC Controller ...................................................................................................................... 6-27
6.6.23. Registers for CIR Controller ....................................................................................................................... 6-27
CHAPTER 7. CONFIGURATION REGISTERS ............................................................................................................... 7-1
7.1. Detailed Description .............................................................................................................................................. 7-1
7.1.1. Detecting G-Bus Timeout ............................................................................................................................... 7-1
7.2. Registers............................................................................................................................................................... 7-2
7.2.1. Chip Configuration Register (CCFG) 0xE000 .......................................................................................... 7-3
7.2.2. Chip Revision ID Register (REVID) 0xE008 ............................................................................................ 7-7
7.2.3. Pin Configuration Register (PCFG) 0xE010............................................................................................. 7-8
7.2.4. Timeout Error Access Address Register (TOEA) 0xE018 .........................................................................7-11
Rev. 3.3 May 18, 2007
ii
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