TX4939 View Datasheet(PDF) - Toshiba
Part Name
Description
Manufacturer
TX4939 Datasheet PDF : 756 Pages
| |||
Index
Toshiba RISC Processor
TX4939
7.2.5. Clock Control Register (CLKCTR) 0xE020 ........................................................................................... 7-12
7.2.6. G-Bus Arbiter Control Register (GARBC) 0xE030 .................................................................................. 7-16
7.2.7. Register Address Mapping Register (RAMP) 0xE048............................................................................. 7-17
7.2.8. DLL De-Skew Control Register (DSKWCTRL) 0xE060 .......................................................................... 7-18
7.2.9. MCLKOSC Register
0xE068............................................................................................................... 7-19
7.2.10. MCLKCTL Register
0xE070.............................................................................................................. 7-20
7.2.11. GPIO Mode Register 1(GPIOMR1) 0xE100 ......................................................................................... 7-21
7.2.12. GPIO Data Register 1 (GPIODR1) 0xE108 ......................................................................................... 7-22
7.2.13. GPIO Mode Register 2(GPIOMR2) 0xE110 ......................................................................................... 7-23
7.2.14. GPIO Data Register 2 (GPIODR2) 0xE118.......................................................................................... 7-24
CHAPTER 8. INTERRUPT CONTROLLER .................................................................................................................... 8-1
8.1. Characteristics ...................................................................................................................................................... 8-1
8.2. Block Diagram....................................................................................................................................................... 8-2
8.3. Detailed Explanation ............................................................................................................................................. 8-4
8.3.1. Interrupt Sources ........................................................................................................................................... 8-4
8.3.2. Interrupt Operation Mode ............................................................................................................................... 8-4
8.3.3. Compatible Mode ........................................................................................................................................... 8-4
8.3.4. Original Mode................................................................................................................................................. 8-4
8.3.5. Interrupt Request Detection ........................................................................................................................... 8-6
8.3.6. Interrupt Level Assigning................................................................................................................................ 8-6
8.3.7. Interrupt Priority Assigning ............................................................................................................................. 8-6
8.3.8. Interrupt Notification of Original Mode............................................................................................................ 8-7
8.3.9. Interrupt Notification of Compatible Mode ...................................................................................................... 8-7
8.3.10. Clearing Interrupt Requests ......................................................................................................................... 8-7
8.3.11. Interrupt requests ......................................................................................................................................... 8-8
8.4. Registers............................................................................................................................................................... 8-9
8.4.1. Interrupt Detection Enable Register (IRDEN) 0xE800 ............................................................................ 8-10
8.4.2. Interrupt Source and Cause IP Binding Register (ISCIPB) 0xE808 ...........................................................8-11
8.4.3. Interrupt Detection Mode Register 0 (IRDM0) 0xE810............................................................................ 8-12
8.4.4. Interrupt Detection Mode Register 1 (IRDM1) 0xE818............................................................................ 8-13
8.4.5. Interrupt Detection Mode Register 2 (IRDM2) 0xE8C8 ........................................................................... 8-14
8.4.6. Interrupt Detection Mode Register3 (IRDM3) 0xE8D0 ............................................................................ 8-15
8.4.7. Interrupt Mask Level Register (IRMSK) 0xE8A0 .................................................................................... 8-16
8.4.8. Interrupt Level Registers (IRLVLxx) ............................................................................................................. 8-17
8.4.9. Interrupt Edge Detection Clear Register (IREDC) 0xE8A8 ...................................................................... 8-18
8.4.10. Interrupt Pending Register 0 (IRPND0) 0xE8B0 .................................................................................. 8-19
8.4.11. Interrupt Pending Register 1 (IRPND1) 0xE8C0 .................................................................................. 8-20
8.4.12. Interrupt Current Status Register (IRCS) 0xE8B8 ................................................................................. 8-21
8.4.13. Interrupt Request Flag Register 0 (IRFLAG0) 0xE900........................................................................... 8-22
8.4.14. Interrupt Request Flag Register 1 (IRFLAG1) 0xE908........................................................................... 8-23
8.4.15. Interrupt Request Polarity Control Register (IRPOL) 0xE910 ................................................................. 8-24
8.4.16. Interrupt Request Control Register (IRRCNT) 0xE918 .......................................................................... 8-25
8.4.17. Interrupt Request Internal Interrupt Mask Register (IRMASKINT) 0xE920 .............................................. 8-26
8.4.18. Interrupt Request External Interrupt Mask Register (IRMASKEXT) 0xE928 ............................................ 8-27
8.4.19. Interrupt Debug Register 0 (IRDBR0) 0xE8D8 .................................................................................... 8-27
8.4.20. Interrupt Debug Register 1 (IRDBR1) 0xE8E0..................................................................................... 8-28
8.4.21. Interrupt Debug Enable Register (IRDBEN) 0xE8E8 ............................................................................ 8-28
CHAPTER 9. EXTERNAL BUS INTERFACE.................................................................................................................. 9-1
9.1. Basic Structure...................................................................................................................................................... 9-1
9.1.1. External Bus Connection Diagram ................................................................................................................. 9-1
9.2. External Bus Controller ......................................................................................................................................... 9-2
9.2.1. External Bus Channel Control Registers........................................................................................................ 9-2
9.2.2. Boot Up Options............................................................................................................................................. 9-2
9.2.3. Address Mapping ........................................................................................................................................... 9-3
9.2.4. External Address Output ................................................................................................................................ 9-4
9.2.5. Address Bit Corresponding in the 16-bit Mode............................................................................................... 9-4
9.2.6. Address Bit Corresponding in the 8-bit Mode................................................................................................. 9-4
9.2.7. Access Mode.................................................................................................................................................. 9-5
9.2.8. Access Timing ................................................................................................................................................ 9-8
9.2.9. Clock Options............................................................................................................................................... 9-14
9.2.10. ISA Mode (16-bit only) ............................................................................................................................... 9-14
9.3. Register Detail..................................................................................................................................................... 9-15
9.3.1. External Bus Channel Control Register (EBCCRn)...................................................................................... 9-15
9.4. Timing Diagrams ................................................................................................................................................. 9-18
Rev. 3.3 May 18, 2007
iii
Share Link: 