TX4939 View Datasheet(PDF) - Toshiba
Part Name
Description
Manufacturer
TX4939 Datasheet PDF : 756 Pages
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Index
Toshiba RISC Processor
TX4939
9.4.1. ACE* Signal ................................................................................................................................................. 9-19
9.4.2. Normal Mode Access (Single, 16-bit bus) .................................................................................................... 9-20
9.4.3. Normal Mode Access (Burst, 16-bit Bus) ..................................................................................................... 9-22
9.4.4. Normal Mode Access (Single, 8-bit Bus)...................................................................................................... 9-23
9.4.5. Normal Mode Access (Burst, 8-bit Bus) ....................................................................................................... 9-25
9.4.6. Page Mode Access (Burst, 16-bit Bus) ........................................................................................................ 9-26
9.4.7. External ACK Mode Access (16-bit Bus)...................................................................................................... 9-27
9.4.8. READY Mode Access (16-bit Bus) ............................................................................................................... 9-32
9.4.9. ISA IO Space Access (16-bit only) ............................................................................................................... 9-33
CHAPTER 10. NAND FLASH MEMORY CONTROLLER............................................................................................. 10-1
10.1. Features............................................................................................................................................................ 10-1
10.2. Block diagram ................................................................................................................................................... 10-2
10.2.1. Theory of Operation ................................................................................................................................... 10-2
10.3. Detailed Operation ............................................................................................................................................ 10-3
10.3.1. Registers.................................................................................................................................................... 10-3
10.3.2. Convention for following explanation.......................................................................................................... 10-3
10.3.3. Accessing NAND Flash Memory (General Procedure) .............................................................................. 10-4
10.3.4. Initialization and UPDATE .......................................................................................................................... 10-5
10.3.5. Write Sequence (8-bit Bus, Program Mode) .............................................................................................. 10-6
10.3.6. Read Sequence (8-bit Bus, Program / DMA Mode) ................................................................................... 10-7
10.3.7. Read ID...................................................................................................................................................... 10-8
10.4. ECC and DMA Operation .................................................................................................................................. 10-9
10.4.1. ECC Generation......................................................................................................................................... 10-9
10.4.2. ECC Data Format..................................................................................................................................... 10-10
10.4.3. DMA Operation ........................................................................................................................................ 10-10
10.4.4. Byte Sequence of DMA and ECC Generation...........................................................................................10-11
10.5. Registers Detail............................................................................................................................................... 10-13
10.5.1. NAND Flash Memory Data Transfer Register (NDFDTR) 0x5000 ........................................................ 10-13
10.5.2. NAND Flash Memory Mode Control Register (NDFMCR) 0x5008 ......................................................... 10-14
10.5.3. NAND Flash Memory Status Register (NDFSR) 0x5010 ..................................................................... 10-15
10.5.4. NAND Flash Memory Interrupt Status Register (NDFISR) 0x5018 ....................................................... 10-15
10.5.5. NAND Flash Memory Interrupt Mask Register (NDFIMR) 0x5020 ........................................................ 10-16
10.5.6. NAND Flash Memory Strobe Pulse Width Register (NDFSPR) 0x5028................................................. 10-17
10.6. Timing diagram ............................................................................................................................................... 10-18
10.6.1. Initialization Sequence ............................................................................................................................. 10-18
10.6.2. Data Read Sequence............................................................................................................................... 10-19
10.6.3. Data Write Cycles .................................................................................................................................... 10-20
CHAPTER 11. REAL TIME CLOCK ...............................................................................................................................11-1
11.1. Feature of Real Time Clock Module (RTC).........................................................................................................11-1
11.2. RTC IP Pin Description.......................................................................................................................................11-2
11.2.1. RTC IP External Pin Description..................................................................................................................11-2
11.3. RTC IP Registers................................................................................................................................................11-3
11.3.1. RTC IP Internal Registers............................................................................................................................11-3
11.3.2. RTC IP Control Registers ............................................................................................................................11-5
11.3.3. Control and Status Register (RTCCTL) 0xFB00.....................................................................................11-5
11.3.4. Address Register (RTCADR) 0xFB04 ..................................................................................................11-6
11.3.5. Data port to access the contents of RTC Register (RTCDAT) 0xFB08 ....................................................11-6
11.3.6. Time Base Corrector Register (RTCTBC) 0xFB0C ................................................................................11-6
11.4. Time Base Calibration ........................................................................................................................................11-7
11.4.1. Theory of Operation ....................................................................................................................................11-7
CHAPTER 12. VIDEO PORT......................................................................................................................................... 12-1
12.1. Feature.............................................................................................................................................................. 12-1
12.2. Block Diagram................................................................................................................................................... 12-2
12.3. Operations ........................................................................................................................................................ 12-3
12.3.1. Video Port DMA Controller ......................................................................................................................... 12-3
12.3.2. 8-bit Parallel port ........................................................................................................................................ 12-4
12.3.3. Serial port................................................................................................................................................... 12-5
12.3.4. Data Format ............................................................................................................................................... 12-6
12.3.5. Transmit Window Option ............................................................................................................................ 12-7
12.3.6. Video Port Controller Registers.................................................................................................................. 12-9
12.3.7. Descriptor Format .................................................................................................................................... 12-14
12.3.8. Big Endian Support .................................................................................................................................. 12-16
Rev. 3.3 May 18, 2007
iv
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