TX4939 View Datasheet(PDF) - Toshiba
Part Name
Description
Manufacturer
TX4939 Datasheet PDF : 756 Pages
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Index
Toshiba RISC Processor
TX4939
CHAPTER 13. TIMER/COUNTER CONTROLLER ....................................................................................................... 13-1
13.1. Features............................................................................................................................................................ 13-1
13.2. Block Diagram................................................................................................................................................... 13-2
13.3. Detailed Explanation ......................................................................................................................................... 13-4
13.3.1. Overview .................................................................................................................................................... 13-4
13.3.2. Counter Clock ............................................................................................................................................ 13-4
13.3.3. Counter ...................................................................................................................................................... 13-5
13.3.4. Interval Timer Mode ................................................................................................................................... 13-5
13.4. Pulse Generator Mode ...................................................................................................................................... 13-7
13.5. Watchdog Timer Mode ...................................................................................................................................... 13-8
13.6. Registers......................................................................................................................................................... 13-10
13.6.1. Timer Control Register n (TMTCRn) .........................................................................................................13-11
13.6.2. Timer Interrupt Status Register n (TMTISRn)........................................................................................... 13-12
13.6.3. Compare Register An (TMCPRAn) .......................................................................................................... 13-14
13.6.4. Compare Register Bn (TMCPRBn) .......................................................................................................... 13-15
13.6.5. Interval Timer Mode Register n (TMITMRn)............................................................................................. 13-16
13.6.6. Divide Register n (TMCCDRn) ................................................................................................................. 13-17
13.6.7. Pulse Generator Mode Register n (TMPGMRn) ...................................................................................... 13-18
13.6.8. Watchdog Timer Mode Register n (TMWTMRn) ...................................................................................... 13-19
13.6.9. Timer Read Register n (TMTRRn) ........................................................................................................... 13-20
CHAPTER 14. DMA CONTROLLER............................................................................................................................. 14-1
14.1. Features............................................................................................................................................................ 14-1
14.2. Block Diagram................................................................................................................................................... 14-2
14.3. Detailed Explanation ......................................................................................................................................... 14-4
14.3.1. Transfer Mode ............................................................................................................................................ 14-4
14.3.2. On-chip Registers ...................................................................................................................................... 14-4
14.3.3. External I/O DMA Transfer Mode ............................................................................................................... 14-5
14.3.4. Internal I/O DMA Transfer Mode................................................................................................................. 14-6
14.3.5. Memory-Memory Copy Mode..................................................................................................................... 14-7
14.3.6. Memory Fill Transfer Mode......................................................................................................................... 14-7
14.3.7. Single Address Transfer ............................................................................................................................. 14-8
14.3.8. Dual Address Transfer.............................................................................................................................. 14-10
14.3.9. DMA Transfer ........................................................................................................................................... 14-14
14.3.10. Chain DMA Transfer............................................................................................................................... 14-15
14.3.11. Dynamic Chain Operation ...................................................................................................................... 14-17
14.3.12. Interrupts ................................................................................................................................................ 14-17
14.3.13. Transfer Stall Detection Function ........................................................................................................... 14-18
14.3.14. Arbitration Among DMA Channels.......................................................................................................... 14-18
14.3.15. Restrictions in Access to PCI Bus .......................................................................................................... 14-19
14.4. DMA Controller Registers................................................................................................................................ 14-20
14.4.1. DMA Master Control Register (DM0MCR, DM1MCR).............................................................................. 14-22
14.4.2. DMA Channel Control Register (DM0CCRn, DM1CCRn) ........................................................................ 14-24
14.4.3. DMA Channel Status Register (DM0CSRn, DM1CSRn)) ......................................................................... 14-28
14.4.4. DMA Source Address Register (DM0SARn, DM1SARn) ......................................................................... 14-30
14.4.5. DMA Destination Address Register (DM0DARn, DM1DARn)................................................................... 14-31
14.4.6. DMA Chain Address Register (DM0CHARn, DM1CHARn) ...................................................................... 14-32
14.4.7. DMA Source Address Increment Register (DM0SAIRn, DM1SAIRn)....................................................... 14-33
14.4.8. DMA Destination Address Increment Register (DM0DAIRn, DM1DAIRn)................................................ 14-34
14.4.9. DMA Count Register (DM0CNTRn, DM1CNTRn) .................................................................................... 14-35
14.4.10. DMA Memory Fill Data Register (DM0MFDR, DM1MFDR).................................................................... 14-36
14.5. Timing Diagrams ............................................................................................................................................. 14-37
14.5.1. External I/O Device – SRAM Dual Address Transfer................................................................................ 14-37
14.5.2. External I/O Device – SRAM Dual Address Transfer................................................................................ 14-39
14.5.3. External I/O Device (Non-burst) – Memory Dual Address Transfer .......................................................... 14-40
CHAPTER 15. DDR SDRAM CONTROLLER ............................................................................................................... 15-1
15.1. Features............................................................................................................................................................ 15-1
15.2. Register Map..................................................................................................................................................... 15-2
15.3. DDR SDRAM Interface ..................................................................................................................................... 15-3
15.3.1. Pin Signals ................................................................................................................................................. 15-3
15.4. Read ................................................................................................................................................................. 15-4
15.4.1. Write........................................................................................................................................................... 15-6
15.5. Precharge ......................................................................................................................................................... 15-8
15.6. Power-Down ..................................................................................................................................................... 15-9
Rev. 3.3 May 18, 2007
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