TZA1020A View Datasheet(PDF) - Philips Electronics
Part Name
Description
Manufacturer
TZA1020A Datasheet PDF : 36 Pages
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Philips Semiconductors
Pre-amplifiers for CD-RW systems
Product specification
TZA1020; TZA1020A
8 I2C-BUS PROTOCOL
8.1 Addressing and data bytes
Full control of the TZA1020 is accomplished via the 2-wire I2C-bus. Up to 400 kbits/s bus speed can be used in
accordance with the I2C-bus fast-mode specification.
For programming the device (write mode) eight data byte registers are available/addressable via eight subaddresses.
Automatic subaddress incrementing enables the writing of successive data bytes in one transmission. During power-on,
data byte registers are reset to a default state by use of a Power-On Reset (POR) circuit whose signal is derived from
the internally generated I2C-bus supply voltage (VSS1).
For reading from the device (read mode) one data byte register is available without subaddressing.
8.1.1 WRITE MODE
Table 1 Slave address; 34H
Slave address
0
0
1
1
0
1
0
0
Table 2 Subaddress 00H to 07H
Subaddress
0(1)
0(1)
0(1)
0(1)
0
0/1
0/1
0/1
Note
1. The use of subaddresses F0H to F7H (11110XXX) instead of 00H to 07H (00000XXX) disables the automatic
subaddress incrementing allowing continuous writing to a single data byte register (e.g. DAC testing).
Table 3 Overview of subaddresses
SUB POR
ADDR STATE
DATA BYTES
00H 00000000 alphactr2 alphactr1 alphactr0 alphagain4 alphagain3 alphagain2 alphagain1 alphagain0
01H 00000000 free
algctr6 algctr5 algctr4
algct3
algctr2
algctr1
algctr0
02H 00000000 tlngain1 tlngain0 rengain negain4 negain3 negain2 negain1 negain0
03H 00000000 tmdac tlnlim1 tlnlim0 sumref4 sumref3 sumref2 sumref1 sumref0
04H 00000000 sdfine7 sdfine6 sdfine5 sdfine4 sdfine3 sdfine2 sdfine1 sdfine0
05H 00011111 lexton betactrl1 betactrl0 betascl4 betascl3 betascl2 betascl1 betascl0
06H 01100000 free ppnctrl1 ppnctrl0 ppnscl4 ppnscl3 ppnscl2 ppnscl1 ppnscl0
07H 00000000 porr
free
urefsel cdrwsel
lpsel1
lpsel0 meassel1 meassel0
8.1.2 READ MODE
Table 4 Slave address; 35H
Slave address
0
0
1
1
0
1
0
1
Table 5 Read byte
Read byte
por(1)
0(2)
0(2)
0(2)
0(2)
0(2)
0(2)
0(2)
Notes
1. In read mode the actual POR status can be read.
2. The state of unused read bits should not be relied upon; their state may be changed during development.
2000 Oct 30
8
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