UPD16364 View Datasheet(PDF) - NEC => Renesas Technology

Part Name

Description

Manufacturer

UPD16364

160-BIT HIGH-VOLTAGE CMOS DRIVER

NEC => Renesas Technology 

µ PD16364

3. PIN FUNCTIONS

Pin Symbol

Pin Name

! EIO1

Enable I/O1

! EIO2

Enable I/O2

SCK

DST

Shift Clock Input

Data Strobe Input

D0 to D7

Data Input

L,/R

Select Left or Right

Shift

OC

Output Control

REV

Invert Input Data

BS

Bus Select

OUT1 to

OUT160

VDD1

VDD2

VSS1

VSS2

High-voltage output

Logic power supply

Driver power supply

Logic ground

Driver ground

I/O

I/O

I/O

Input

Input

Input

Input

Description

L,/R pin = “L” level: Input

L,/R pin = “H” level: Output

L,/R pin = “H” level: Input

L,/R pin = “L” level: Output

Fall edge operation. Input shift clock for 4 x 40/8 x 20-bit data latch.

Fall edge operation. Data are latched to 160-bits data latch and also set

outputs of OUT1 to OUT160.

Data input. When BS is low level, D4 to D7 pins should be connected to VSS1

or VDD1.

Refer to 4.TRUTH TABLE

Input

Input

Input

Output

–

–

–

–

When OC pin is low level, output is normal operation.

When OC pin is high level, output become low level.

When REV pin is low level, input data D0 to D7 are latched without inversion.

When REV pin is high level, input data D0 to D7 are inverted before latching.

When BS pin is low level, data bus is4 bits.

When BS pin is high level, data bus is 8 bits.

Output level is VSS2 or VDD2. These outputs are changed by falling edge of

DST pin.

Logic power supply

Driver power supply

Grounding

Grounding

4

Data Sheet S14000EJ2V0DS

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