UPD16434G-001-12 View Datasheet(PDF) - NEC => Renesas Technology

Part Name

Description

Manufacturer

UPD16434G-001-12

1/8/ 1/15 DUTY LCD CONTROLLER/DRIVER

NEC => Renesas Technology 

µ PD16434

1.11 SYNC (Synchronous) … 3-state input/output

In a multi-chip configuration, in which the row drive signal is commonly used, this pin inputs/outputs the

synchronous signal in order to synchronize the phases of all LCD drive alternate cycle signals (row/column signals)

with the frame period.

One chip in the multi-chip configuration is selected as the master, and the SYNC pin of the master is set to the

output mode.

The remaining chips all serve as slave chips, and these SYNC pins are set to the input mode.

The SMM command is used to specify whether the pin functions as an input or output pin.

The master chip, set in the output mode, outputs the SYNC pulse in the last cycle in each frame. A slave chip

reads the SYNC pulse output from the master chip for synchronization with the master chip.

Figure 1-1 and Figure 1-2 show SYNC pulse output timing waveforms in 8-time-division and 16-time-division

modes, respectively.

In single chip configuration, the SYNC pin can be set in either the input or output mode. However, when it is set in

the input mode, the SYNC pin must be fixed to VSS. If it is set in the output mode, the SYNC pin must be left open.

Figure 1–1. SYNC Signal in 8-Time-Division Mode

1 frame

ROW0

SYNC

ROW0

Figure 1–2. SYNC Signal in 16-Time-Division Mode

1 frame

SYNC

8

Data Sheet S10299EJ4V0DS00

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