UPD16635 View Datasheet(PDF) - NEC => Renesas Technology
Part Name
Description
Manufacturer
UPD16635 Datasheet PDF : 19 Pages
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µPD16635
4. PIN FUNCTIONS
Pin Symbol
S1 to S240
D00 to D05
D10 to D15
D20 to D25
D31 to D35
D40 to D45
D50 to D55
R/L
Pin Name
Driver output
Display data input
Shift direction
switching input
STHR
STHL
CLK
Right shift start
pulse input/output
Left shift start
pulse input/output
Shift clock input
STB
POL
Latch input
Polarity input
V0 to V9
TEST
VDD1
VDD2
VSS1
VSS2
γ -corrected power
supplies
Test pin
Logic power supply
Driver power supply
Logic ground
Driver ground
Description
The D/A converted 64-gray-scale analog voltage is output.
The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by
6 dots (2 pixels).
DX0: LSB, DX5: MSB
These refer to the start pulse input/output pins when cascades are connected.
The shift directions of the shift registers are as follows.
R/L = H: STHR input, S1 → S240, STHL output
R/L = L : STHL input, S240 → S1, STHR output
R/L = H: Becomes the start pulse input pin.
R/L = L : Becomes the start pulse output pin.
R/L = H: Becomes the start pulse output pin.
R/L = L : Becomes the start pulse input pin.
Refers to the shift register’s shift clock input. The display data is incorporated into
the data register at the rising edge. At the rising edge of the 40th clock after the
start pulse input, the start pulse output reaches the high level, thus becoming the
start pulse of the next-stage driver. The initial-stage driver’s 40th clock becomes
valid as the next-stage driver’s start pulse is input. If 42 clock pulses are input
after input of the start pulse, input of display data is halted automatically. The
contents of the shift register are cleared at the STB’s rising edge.
The contents of the data register are transferred to the latch at the rising edge.
And, at the falling edge, the gray scale voltage is supplied to the driver. It is
necessary to ensure input of one pulse per horizontal period.
POL = L; The S2n–1 output uses V0 to V4 as the reference supply; and the S2n
output uses V5 to V9 as the reference supply.
POL = H; The S2n–1 output uses V5 to V9 as the reference supply; and the S2n
output uses V0 to V4 as the reference supply.
S2n – 1 indicates the odd output; and S2n indicates the even output.
Input of the POL signal is allowed the setup time (tPOL-STB) with respect to STB’s
rising edge.
Input the γ -corrected power supplies from outside. Make sure to maintain the
following relationships. During the gray scale voltage output, be sure to keep the
gray scale level power supply at a constant level.
VDD2 > V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > V8 > V9 > VSS2
Set it to “OPEN”.
3.3 V ± 0.3 V
11.0 V to 13.5 V
Grounding
Grounding
Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V9 in that order. Reverse
this sequence to shut down. (Simultaneous power application to VDD2 and V0 to V9 is possible.)
2. To stabilize the supply voltage, please be sure to insert a 0.1 µF bypass capacitor between
VDD1-VSS1 and VDD2-VSS2. Furthermore, for increased precision of the D/A converter, insertion
of a bypass capacitor of about 0.01 µF is also advised between the γ -corrected power supply
terminals (V0, V1, V2, ···, V9) and VSS2.
5
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