UPD16663 View Datasheet(PDF) - NEC => Renesas Technology

Part Name

Description

Manufacturer

UPD16663

240-OUTPUT LCD COLUMN (SEGMENT) DRIVER WITH BUILT-IN RAM

NEC => Renesas Technology 

µPD16663

2. BLOCK FUNCTION

(1) Address management circuit

Converts an address transferred from the system via A0 to A16 to an address that corresponds to the on-

chip RAM memory map.

This function enables address management for a display size of up to 480 x 320 dots using four µPD16663

LSIs, thus facilitating the configuration of LCD systems.

The allocation of addresses 1FFF80H to 1FFFEH (even addresses only) to the gray scale palette register

also allows the user to select any 16 gray scales from a palette of 49.

(2) Arbiter

Resolves a conflict between a RAM access from the system and a RAM read on the LCD drive side.

(3) RAM

240 x 160 x 4 bits of static RAM (single port).

(4) Data bus control

Controls the direction in which data is transferred according to whether the system is reading or writing.

The bus width can also be switched between 8 and 16 bits with the BMODE pin.

(5) Gray scale generation circuit

Culls frames and modulates the pulse width to realize 49 gray scales.

(6) Internal timing generator

Generates the internal timing for each block from the /FRM and STB signals.

(7) CR oscillator

In master mode, this oscillator generates the clock referenced for the frame frequency. The frame frequency

is determined by dividing this clock by 2592. To obtain a frame frequency of 70 Hz, therefore, an oscillation

frequency of 181.44 kHz is required. Because the CR oscillator is on chip, adjust the oscillation frequency

using an external resistor.

Oscillation is stopped in slave mode.

(8) LCD timing generator

In master mode, this generator generates /FRM (the frame signal), STB (the column driver signal strobe),

and PULSE (the 49-gray-scale pulse modulation clock).

(9) Gray scale control

This is a circuit for realizing a 16-gray-scale display.

4

Data Sheet S13392EJ1V0DS00

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