UPD16675A View Datasheet(PDF) - NEC => Renesas Technology
Part Name
Description
Manufacturer
UPD16675A Datasheet PDF : 36 Pages
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µPD16675A
1. PIN FUNCTIONS
1.1 Power System
Pin Symbol
Pin Name
VDD1
Logic power supply
pin
VDD2
Power supply pin for
booster circuit
VSS
Logic ground pin
VLCD
Driver power supply
pin
VLC1 to VLC5
C1+, C1−,
C2+, C2−
VEE
Driver reference
power supply
Capacitor connection
pins
Driver ground pin
Pin No. I/O
203, 204, ---
224
197
---
206, 221, ---
222
180, 181 ---
179 to 175 ---
185 to 196 ---
228, 229 ---
Description
Power supply pin for logic
Power supply pin for booster circuit. Set the pin to
VDD1 ≤ VDD2.
Ground pin for logic
Driver power supply pin. Output pin of internal
booster circuit. Connect with a 1-µF booster
capacitor to the VDD2 pin.
When not using the internal booster circuit, the
driver power can be turned on directly.
Reference power supply pin for LCD drive. When
the internal bias is selected, be sure to leave it open.
Capacitor connection pins for booster circuit.
Connect a 1 µF capacitor.
Ground pin for driver
1.2 Logic System
Pin Symbol
Pin Name
Pin No. I/O
Description
WS
Word length selection 223
I
This pin selects the word length. At High level, it
becomes an 8-bit parallel interface. At Low level, it
becomes a 4-bit parallel interface if D7/NS is High;
and a serial interface if D7/NS is Low. When the
word length is 4 bits, data is transferred in the upper-
to-lower sequence by means of data buses D0 to D3.
The word length cannot be changed after power-on.
STB
Strobe
220
I
Data can be input/output at Low level either in
parallel interface or serial interface mode.
E/SCK
Enable/shift clock
219
I
In parallel interface mode, this becomes the data
enable input pin. During read-in, data is fetched into
the interface buffer at the rising edge. During read-
out, data is fetched from the interface buffer at the
falling edge.
In serial interface mode, this pin becomes the data
shift clock. During read-in, data is fetched into the
shift register at the rising edge. During read-out,
data is fetched from the shift register at the falling
edge.
CLKOUT
Clock for slave IC
226
output
O
This pin outputs an inverted oscillation clock. It
connects to slave IC’s OSCIN directly.
POCOUT
Power-on reset
monitor
225
O
Monitor pin for internal power-on reset.
At Low level, power-on reset is set internally. At
Low level, power-on reset is released.
The pin is for IC testing. Normally leave it open.
6
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