UPD16675A View Datasheet(PDF) - NEC => Renesas Technology

Part Name

Description

Manufacturer

UPD16675A

1/34, 1/36 DUTY LCD CONTROLLER/DRIVER

NEC => Renesas Technology 

µPD16675A

1.2 Logic System (Continued)

Pin Symbol

Pin Name

D0/DATA

Data bus/data

Pin No. I/O

218

I/O

D1 to D5

D6/CAE

Data bus

Data bus/chip

address enable

217 to 213 I/O

212

I/O

D7/NS

Data bus/nibble select 211

I/O

_____________

RESET

VCHA

DACHA

VEXT

SYNC

Reset

210

I

Boosting magnitude

205

I

switching

D/A converter

switching

202

I

Reference supply

198

I

switching

Synchronization

227

I/O

CS0 to CS2

Chip select

207 to 209 I

OSCIN

OSCOUT

OSCBRI

Oscillation pin

200

I

201

O

External clock for

199

I

blinks

Description

In parallel interface mode, this pin becomes the D0

bit of the data bus.

In serial interface mode, it becomes the input/output

pin of the command and display data (3 states).

In parallel interface mode, these pins become the D1

to D5 bits of the data bus.

In serial interface mode, leave them open.

In 8-bit parallel interface mode, this pin becomes the

D6 bit of the data bus.

In 4-bit parallel interface and serial interface modes,

it becomes chip address enable. Also, at High level,

it becomes chip address valid; at Low level, chip

address invalid.

In 8-bit parallel interface, it becomes chip address

valid.

When the word select (WS) is High level, this bit

becomes the D7 bit of the data bus.

When WS is Low level, it becomes the nibble select

(NS). When NS is High level, it becomes 4-bit

parallel interface. When NS is Low level, it becomes

serial interface.

In 4-bit parallel interface mode, data cannot be read

out.

At Low level, internal initialization is performed.

The boosting magnitude of the internal booster

circuit is switched over. At High level, it is switched

to 3X, while, at Low level, 2X.

Select whether to use the internal D/A converter for

temperature correction or not. At High level, this

circuit is used, at Low level, unused.

Selects the method for supplying the reference

power circuit. At High level, the circuit is supplied

externally; and, at Low level, internally.

Input/output pin for synchronization.

Master mode: Output

Slave mode: Input

When used for multiple chips, these pins are used to

specify their addresses. They can be accessed only

when coinciding with b2 to b4 bits of the interface

control register.

These pins are connected with the 1 MΩ resistor.

When using external oscillation, input it into the

OSCIN, leaving the OSCOUT open.

Input pin of the 2-Hz external clock.

It internally divides this clock by 2 to generate 1 Hz

and make it the synchronizing signal for blinks.

7

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