UPD16700 View Datasheet(PDF) - NEC => Renesas Technology

Part Name

Description

Manufacturer

UPD16700

256-OUTPUT TFT-LCD GATE DRIVER

NEC => Renesas Technology 

µ PD16700

3. PIN FUNCTIONS

Pin Symbol

Pin Name

I/O

Description

O1 to O256

Driver

O

These pins output scan signals that drive the vertical direction (gate lines) of a

TFT-LCD. The output signals change in synchronization with the rising edge of

shift clock (CLK). The driver output amplitude is VDD2 - VEE2.

R,/L

Shift direction select

I

Refers to the shift direction control. The shift directions of shift registers are as

follows.

R,/L = H (right shift) : STVR → O1 → O256 → STVL

R,/L = L (left shift) : STVL → O256 → O1 → STVR

STVR,

Start pulse

I/O These refer to the input pins of the internal shift register. The start pulse is read

STVL

at the rising edge of CLK, and scan signals are output from the driver output pins.

The input level is a CMOS (3.3 V) level. The start pulse is output at the falling

edge of the 256th clock of CLK, and is cleared at the falling edge of the 257th



clock. The output level is VDD1 - VSS (logic level). The output level is a CMOS

level (3.3 V).

CLK

Shift clock

I

This pin inputs a shift clock to the internal shift register.

The shift operation is performed in synchronization with the rising edge of this

input.

OE1 to OE3 Output enable



I

When these pins go H, the driver output is fixed to VEE2 level.

The shift registers are not cleared. These pins are not synchronous with CLK.

OE1: O1, O4, ... O250, O253, O256

OE1: O2, O5, ... O251, O254

OE1: O3, O6, ... O252, O255

/AO



All-on control

I

When this pin goes L, the driver output is fixed to VDD2 level. The shift register is

not cleared. This pin has priority over OE1 to OE3. This pin is not synchronous

with CLK.

VDD1

Logic power supply

−

3.3 V ± 0.3 V

VDD2

Driver positive power −

15 to 25 V

supply

The driver output : H level

VSS

Logic ground

−

Connect this pin to the ground of the system.

VEE1

Negative Power

−

–15 to –5 V

supply for internal

operation

VEE2

Driver negative

−

The driver output : L level (VEE2-VEE1 < 6.0 V)

power supply

Cautions 1. To prevent latch up, turn on power to VDD1, VEE1/2, VDD2, and logic input in this order. Turn off

power in the reverse order. These power up/down sequence must be observed also during

transition period.

2. Insert a capacitor of about 0.1 µF between each power line, as shown below, to secure noise

margin such as VIH and VIL.

VDD2

VDD1

VSS

VEE1/2

0.1 µF

0.1 µF

0.1 µF

4

Data Sheet S14085EJ3V0DS

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