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UPD17217CT-XXX View Datasheet(PDF) - NEC => Renesas Technology

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Description
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UPD17217CT-XXX Datasheet PDF : 84 Pages
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µPD17215, 17216, 17217, 17218
2.5 Register File (RF)
The register file mainly consists of registers that set the conditions of the peripheral hardware.
These registers can be controlled by dedicated instructions PEEK and POKE, and the embedded macro instructions of
AS17K, SETn, CLRn, and INITFLG.
2.5.1 Configuration of register file
Fig. 2-8 shows the configuration of the register file and how the register file is accessed by the PEEK and POKE
instructions.
The control registers are controlled by using dedicated instructions PEEK and POKE. Since the control registers are
assigned to addresses 00H-3FH regardless of the bank, the addresses 00H-3FH of the general-purpose data memory
cannot be accessed when the PEEK or POKE instruction is used.
The addresses that can be accessed by the PEEK and POKE instructions are the addresses 00H-3FH of the control
registers and 40H-7FH of the general-purpose data memory. The register file consists of these addresses.
The control registers are assigned to addresses 80H-BFH on the IE-17K to facilitate debugging.
Fig. 2-8 Register File Access with PEEK or POKE Instructions
Column address
0 1 2 3 4 5 6 7 8 9 ABCDEF
0
1
Data memory
2
3
4
5
POKE M063, WR
6
7
System register
0
PEEK WR, SP
1
2
POKE LCDMD, WR
3
Control register
Register file
21

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