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UPD17244 View Datasheet(PDF) - NEC => Renesas Technology

Part Name
Description
Manufacturer
UPD17244 Datasheet PDF : 102 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
µPD17240, 17241, 17242, 17243, 17244, 17245, 17246
DIFFERENCES BETWEEN µPD17246 SUBSERIES, µPD17236 SUBSERIES, AND µPD17255
SUBSERIES (2/2)
Item
STOP mode release
condition
Carrier frequency
(fX = 4 MHz)
NRZ low-level period
setting modulo register
(NRZLTMM) and NRZ
high-level period setting
modulo register
(NRZHTMM)
µPD17246 Subseries
µPD17236 Subseries
µPD17225 Subseries
<1> When any of pins P0A0
to P0A3 goes low
<2> When pins P0B0 to P0B3,
P0C0 to P0C3, and P0D0
to P0D3 are used as input
pins and when any of
them goes low
<3> When an interrupt
request (IRQ) of the
interrupt for which the IP
flag is set is generated at
the rising edge or falling
edge of the INT pin
<4> When P0E0 to P0E3 are
used as input pins when
a key matrix is used and
when any of these pins
goes low
<5> When P1A0 to P1A2 and
P1B0 are used as input
pins when a key matrix is
used and when the level
of any of these pins
equals the set clear level
<1> When any of pins P0A0
to P0A3 goes low
<2> When pins P0B0 to P0B3,
P0C0 to P0C3, and P0D0
to P0D3 are used as
input pins and when any
of them goes low
<3> When an interrupt
request (IRQ) of the
interrupt for which the IP
flag is set is generated
at the rising edge or
falling edge of the INT
pin
When any of pins P0A0 to
P0A3 and P0B0 to P0B3 goes
low
Selected by register file
(after reset: fX/2)
<1> If carrier generation clock
is fX/2: 3.9 kHz to 1 MHz
<2> If carrier generation clock
is fX: 7.8 kHz to 2 MHz
<3> If carrier generation clock
is 2fX: 15.6 kHz to 4 MHz
Selected by mask option
<1> If carrier generation
clock is fX/2: 7.8 kHz to
1 MHz
<2> If carrier generation
clock is fX: 15.6 kHz to
2 MHz
7.8 kHz to 1 MHz
NRZLTMM: 8 bits
(REM output control bit is bit
1 of register file at address
12H)
NRZHTMM: 8 bits
NRZLTMM: 7 bits (bit 7 is REM output control bit)
NRZHTMM: 7 bits (bit 7 is fixed to 0)
4
Data Sheet U15002EJ1V0DS

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