UPD161830 View Datasheet(PDF) - NEC => Renesas Technology
Part Name
Description
Manufacturer
UPD161830 Datasheet PDF : 24 Pages
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µPD161830
3. PIN FUNCTIONS
(1/2)
Pin Symbol
Pin Name
Pad No. I/O
Description
S1 to S240
D00 to D05
D10 to D15
D20 to D25
R,/L
STHR
STHL
CLK
STB
Driver output
1 to 240 Output The D/A converted 64-gray-scale analog voltage is output.
Display data input 308 to 303 Input The display data is input with a width of 18 bits, viz., the gray scale data (6 bits) by 3
302 to 297
277 to 272
dots (1 pixels).
DX0: LSB, DX5: MSB
Shift direction
264
Input These refer to the shift direction control input.
control input
The shift directions of the shift registers are as follows.
R,/L = L (left shift): STHL (input), S240 → S1 → STHR (output)
R,/L = H (right shift) : STHR (input), S1 → S240 → STHL (output)
Right shift start 325
I/O These refer to the start pulse I/O pins when driver ICs are connected in cascade.
pulse input/output
Fetching of display data starts when H is read at the rising edge of CLK.
Left shift start
249
I/O R,/L = L (left shift): STHL input, STHR output
pulse input/output
R,/L = H (right shift): STHR input, STHL output
Shift clock input 278
Input This pin is the shift clock input of the shift register.
Display data is captured into the data register at the rising edge.
The start pulse output enters high level at the rising edge of the 80 th clock following
the start pulse input, and becomes the start pulse of the next level driver. The 81th
clock of the first driver becomes the start pulse input of the next driver
Latch input
271
Input A timing signal that latches the contents of the data register. When an H level is read
at the rising edge of CLK, the contents of the data register are latched and transferred
to the D/A converter, and analog voltage corresponding to the display data is output.
Also, because the internal operation via CLK continues even after the STB latch, do
not stop CLK. The contents of the shift register are cleared at the rising edge of STB.
Following a 1-pulse input at startup, this IC will operate normally. Note that the output
switch is turned off at the rising edge of STB.
For the STB input timing, refer to Switching Characteristics Waveform.
POL
INV
VCOM
Polarity inversion 269
signal
Data inversion 296
COM amplitude 248
output
Input This pin inverts the output polarity. The polarity inversion signal data is captured at the
rising edge of STB. The γ -resistor is switched in accordance with the positive/negative
polarity.
POL = L: Negative polarity
POL = H: Positive polarity
Input This pin inverts the input data. Input data in synchronization with the shift clock.
INV = L: Normal input
INV = H: Data inversion input
Output This pin inverts the signal input from the POL pin and outputs it following conversion to
the VDD2 potential at the rising edge of STB. When the VCOM output is not used, VCsel
must be fixed to L.
VCsel
CM
COM amplitude 263
output fixing signal
8-color display 268
mode switching
Input
Input
The VCOM output is fixed to L. When the VCOM output is not used, VCsel needs to be
fixed to L.
VCsel = L: VCOM output fixed to L
VCsel = H: VCOM signal output in correspondence with POL signal
The operating mode is switched to 8-color mode. Input data MSB leads display data.
In this mode, turn off the γ -resistor, amplifier, and BIAS circuit. However, when the γ -
correction power supply is input externally, the γ -circuit current will flow continuously.
CM = L: Normal display mode
CM = H: 8-color display mode
6
Preliminary Product Information S16240EJ2V0PM
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