UPD6125A View Datasheet(PDF) - NEC => Renesas Technology
Part Name
Description
Manufacturer
UPD6125A Datasheet PDF : 40 Pages
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µPD6125A, 6126A
5. DATA POINTER (R0)
R0 (R10, R00) for the data memory can serve as the data pointer for the ROM.
R0 specifies the low-order 8 bits in the ROM address. The high-order 2 bits in the ROM address are specified by
the control register.
Table referencing for ROM data can be easily executed by calling the ROM contents by setting the ROM address
to the data pointer.
When “all clear” is input or on reset, it becomes undefined.
Figure 5-1. Data Pointer Organization
Control registers
(P1 )
AD 9 AD 8
R10
R00
AD 7 AD 6 AD 5 AD 4 AD 3 AD 2 AD 1 AD 0 R 0
6. ACCUMULATOR (A) ……… 4 BITS
The accumulator (A) is a 4-bit register. The accumulator plays a major role in each operation.
When “all clear” is input or on reset, it becomes undefined.
Figure 6-1. Accumulator Organization
A3
A2
A1
A0
A
7. ARITHMETIC LOGIC UNIT (ALU) ……… 4 BITS
The arithmetic logic unit (ALU) is a 4-bit operation circuit, and executes simple operations, such as arithmetic
operations.
8. FLAGS
(1) Status flag
When the status for each pin is checked by the STTS instruction, if the condition coincides with the condition
specified by the STTS instruction, the status flag (F) is set (to 1).
When “all clear” is input or on reset, it becomes undefined.
(2) Carry flag
When the INC (increment) instruction or the RL (rotate left) instruction is executed, if a carry is generated from
the MSB for the accumulator, the carry flag (C) is set (to 1).
The carry flag (C) is also set (to 1), if the contents for the accumulator are “FH”, when the SCAF instruction is
executed.
When “all clear” is input or on reset, it becomes undefined.
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