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UPD62 View Datasheet(PDF) - NEC => Renesas Technology

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UPD62 Datasheet PDF : 64 Pages
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µPD62
3.4 Control Register 1 (P4)
Control register 1 consists of 8 bits. The contents that can be controlled are as shown below.
When reset, the register becomes 0010 0110B.
Table 3-6. Control Register 1 (P4)
Bit
Name
b7
Set
0
value
1
When reset
Fixed
to “0”
0
b6
Fixed
to “0”
0
b5
b4
b3
KI
S0/S1
Pull-down Pull-down
OFF OFF Fixed
ON
ON
to “0”
1
0
0
b2
b1
S1/LED KI/O
mode mode
S1
IN
LED OUT
1
1
b0
S0
mode
OFF
IN
0
b0 : Specifies the input mode of the S0 port. “0” = OFF mode (high impedance); “1” = IN (INPUT mode).
b1 : Specifies the I/O mode of the KI/O port.
“0” = IN (INPUT mode); “1” = OUT (OUTPUT mode).
b2 : Specifies the I/O mode of the S1/LED port. “0” = S1 (INPUT mode); “1” = LED (output mode).
b4 : Specifies the availability of the pull-down resistor in S0/S1 port INPUT mode. “0” = OFF (unavailable);
“1” = ON (available)
b5 : Specifies the availability of the pull-down resistor in KI port. “0” = OFF (unavailable);
“1” = ON (available).
Remark In OUTPUT mode or in OFF mode, all the pull-down resistors are automatically disconnected.
18
Data Sheet U14208EJ1V0DS00

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