UPD75112GF-XXX-3BE View Datasheet(PDF) - NEC => Renesas Technology
Part Name
Description
Manufacturer
UPD75112GF-XXX-3BE Datasheet PDF : 56 Pages
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µPD75112(A), 75116(A)
3.2 Non-Port Pins
Input/Output
Dual
Function
Pin
Function
PTH00 to PTH03
Input
Threshold voltage ariable 4-bit analogy input port.
TI0
TI1
PTO0
PTO1
SCK
SO
SI
INT4
INT0
INT1
INT2
Input
Input/output
Input/output
Input/output
Input
Input
Input
Input
External event pulse input for the timer/event counter or edge
detect vector interrupt input. 1-bit input enable.
P20 Timer/event counter output.
P21
P01 Serial clock input/output.
P02 Serial data output.
P03 Serial data input.
P00 Edge detect vector interrupt input (for detecting both rising and
falling edges).
P10 Edge detect vector interrupt input (detected edge selectable).
P11
P12 Edge detect testable input (for rising edge detection).
INT3
PCL
X1, X2
Input/output
P13
P22 Clock output.
Crystal/ceramic connect pin (system clock oscillation).
In case with the external clock, input a signal to X1 and the
antiphase to X2.
RESET
NC*2
VDD
VSS
Input
System reset input (low level active).
No Connection
Positive power supply.
GND potential.
At Reset
I/O
Circuit
Type*1
N
B
Input
E
Input
F
Input
E
Input
B
Input
B
Input
B
Input
B
Input
E
B
* 1: Circles indicate Schmitt trigger inputs.
2: When the PWB is shared with the µPD75P116, connect the NC pin to VDD directly.
8
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