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UPD75238GJ View Datasheet(PDF) - NEC => Renesas Technology

Part Name
Description
Manufacturer
UPD75238GJ
NEC
NEC => Renesas Technology NEC
UPD75238GJ Datasheet PDF : 190 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
µPD75238
1.2 NON-PORT PINS (2/2)
Pin name
TI0
PTO0
PCL
BUZ
SCK0
SO0/SB0
SI0/SB1
INT4
INT0
INT1
INT2
SCK1
SO1
SI1
AN0-AN3
AN4-AN7
AVDD
AVREF
AVSS
X1, X2
XT1
XT2
RESET
PPO
VDD (3 pins)
VSS (2 pins)
VLOAD
Also
I/O used as
Function
I/ONote
When reset circuit
type
I
P13 External event pulse input for timer/event counter #0 and
event counter #1.
O
P20 Timer/event counter output
Input
O
P22 Clock output
Input
O
P23
Fixed frequency output (for buzzer or system clock trimming) Input
I/O
P01 Serial clock I/O
Input
I/O
P02 Serial data output or serial bus I/O
I/O
P03 Serial data input or serial bus I/O
Input
Input
I
P00 Edge detection vectored interrupt input (Either a rising or
falling edge is detected.)
I
P10 Edge detection vectored interrupt input
Synchronous
P11
(The edge to be detected is selectable.)
Asynchronous
I
P12 Edge detection testable input
Asynchronous
(An rising edge is detected.)
I/O
P81 Serial clock I/O
Input
O
P82 Serial data output
Input
I
P83 Serial data input
Input
I
Analog input to A/D converter
P90-P93
Power supply for A/D converter
I
A/D converter reference voltage input
A/D converter reference GND
I
Connection to a crystal/ceramic resonator for main system
clock generation. When external clock is used, it is input to
X1, and its inverted signal is input to X2.
I
Connection to a crystal resonator for subsystem clock
generation. When external clock is used, it is input to XT1,
and XT2 is left open.
I
System reset input
O
P80 Timer/pulse generator pulse output
Input
Positive power supply
GND potential
Pull-down resistor connection for the FIP controller/driver,
or power supply
B-C
E-B
E-B
E-B
F-A
F-B
M-C
B
B-C
B-C
F
E
B
Y
Y-A
Z
B
Note The circuits enclosed in circles have a Schmitt-triggered input.
10

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