UPD75238GJ View Datasheet(PDF) - NEC => Renesas Technology
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Description
Manufacturer
UPD75238GJ Datasheet PDF : 190 Pages
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µPD75238
3.4 GENERAL REGISTERS: 8 × 4 BITS × 4 BANKS
The general registers are mapped to particular addresses in data memory. Four banks of registers are
provided, with each bank consisting of eight 4-bit registers (B, C, D, E, H, L, X, A).
The register bank (RB) to be enabled at the time of instruction execution is determined by RB = RBE• RBS:
(RBS = 0 to 3)
Each general register allows 4-bit manipulation. In addition, BC, DE, HL, or XA serves as a register pair
for 8-bit manipulation. DL also makes a register pair as well as DE and HL; these three register pairs can be
used as data pointers.
A general register area can be addressed and accessed as normal RAM, regardless of whether it is used
as a register.
Fig. 3-5 General Register Format
Address 3 Data memory 0
3
000H
A register
001H
X register
3
002H
003H
004H
005H
L register
H register
E register
D register
3
Register bank 0
3
006H
C register
007H
B register
008H
00FH
Same as bank 0
Register bank 1
010H
017H
Same as bank 0
Register bank 2
018H
01FH
Same as bank 0
Register bank 3
Fig. 3-6 Register Pair Format
0
B
3
0
C
0
D
0
H
3
0
E
3
0
L
0
X
3
0
A
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