(2) Legend for operation description
A
: A register; 4-bit accumulator
B
: B register
C
: C register
D
: D register
E
: E register
H
: H register
L
: L register
X
: X register
XA
: Register pair (XA); 8-bit accumulator
BC
: Register pair (BC)
DE
: Register pair (DE)
HL
: Register pair (HL)
XA’
: Expanded register pair (XA’)
BC’
: Expanded register pair (BC’)
DE’
: Expanded register pair (DE’)
HL’
: Expanded register pair (HL’)
PC
: Program counter
SP
: Stack pointer
CY
: Carry flag; Bit accumulator
PSW : Program status word
MBE : Memory bank enable flag
RBE : Register bank enable flag
PORTn : Port n (n = 0 to 6)
IME : Interrupt master enable flag
IPS
: Interrupt priority select register
IE××× : Interrupt enable flag
RBS : Register bank select register
MBS : Memory bank select register
PCC : Processor clock control register
•
: Address and bit delimiter
(××)
: Contents addressed by ××
××H
: Hexadecimal data
µPD75212A
35