µPD754302, 754304, 754302(A), 754304(A)
6.2 Clock Generator
• Clock generator configuration
The clock generator provides the clock signals to the CPU and peripheral hardware and its configuration
is shown in Figure 6-1.
The operation of the clock generator is set with the processor clock control register (PCC).
The instruction execution time can be changed.
• 0.95, 1.91, 3.81, 15.3 µs (system clock operating at 4.19 MHz)
• 0.67, 1.33, 2.67, 10.7 µs (system clock operating at 6.0 MHz)
Figure 6-1. Clock Generator Block Diagram
X1
System
fX
clock oscillator
X2
Oscillation
stop
PCC
PCC0
PCC1
4
PCC2
HALTNote
PCC3
STOPNote
· Basic interval timer (BT)
· Timer/event counters 0, 1
· Serial interface
· INT0 noise eliminator
· Clock output circuit
1/2 1/4 1/16
1/1 to 1/4096
Divider
Selector
Divider
1/4
Φ
· CPU
· INT0 noise eliminator
· Clock output circuit
HALT F/F
S
RQ
PCC2,
PCC3
Clear
STOP F/F
QS
R
Note Instruction execution
Wait signal from BT
RESET signal
Standby release signal from
interrupt control circuit
Remarks 1.
2.
3.
4.
fX = System clock frequency
Φ = CPU clock
PCC: Processor Clock Control Register
One clock cycle (tCY) of the CPU clock is equal to one machine cycle of the instruction.
21