UPD75P0076GT View Datasheet(PDF) - NEC => Renesas Technology
Part Name
Description
Manufacturer
UPD75P0076GT Datasheet PDF : 62 Pages
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µPD75P0076
1. PIN CONFIGURATION (Top View)
• 42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
µPD75P0076CU
• 42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)
µPD75P0076GT
XT1
1
XT2
2
RESET
3
X1
4
X2
5
P33/MD3
6
P32/MD2
7
P31/MD1
8
P30/MD0
9
AVSS
10
P63/KR3/AN7
11
P62/KR2/AN6
12
P61/KR1/AN5
13
P60/KR0/AN4
14
P113/AN3
15
P112/AN2
16
P111/AN1
17
P110/AN0
18
AVREF
19
VPP
20
VDD
21
42
VSS
41
P40/D0
40
P41/D1
39
P42/D2
38
P43/D3
37
P50/D4
36
P51/D5
35
P52/D6
34
P53/D7
33
P00/INT4
32
P01/SCK
31
P02/SO/SB0
30
P03/SI/SB1
29
P10/INT0
28
P11/INT1
27
P12/TI1/INT2
26
P13/TI0
25
P20/PTO0
24
P21/PTO1
23
P22/PCL
22
P23/BUZ
In normal operation mode, make sure to connect VPP directly to VDD.
Pin Identification
AN0 to AN7
: Analog Input 0 to 7
AVREF
: Analog Reference
AVSS
: Analog Ground
BUZ
: Buzzer Clock
D0 to D7
: Data Bus 0 to 7
INT0, INT1, INT4 : External Vectored Interrupt 0, 1, 4
INT2
: External Test Input 2
KR0 to KR3
: Key Return
MD0 to MD3
: Mode Selection 0 to 3
P00 to P03
: Port 0
P10 to P13
: Port 1
P20 to P23
: Port 2
P30 to P33
: Port 3
P40 to P43
: Port 4
P50 to P53
: Port 5
P60 to P63
: Port 6
P110 to P113 : Port 11
PCL
: Programmable Clock
PTO0, PTO1 : Programmable Timer Output 0, 1
RESET
: Reset Input
SB0, SB1 : Serial Data Bus 0, 1
SCK
: Serial Clock
SI
: Serial Input
SO
: Serial Output
TI0, TI1
: Timer Input 0, 1
VDD
: Positive Power Supply
VPP
: Programmable Power Supply
VSS
: Ground
X1, X2
: Main System Clock Oscillation 1, 2
XT1, XT2 : Subsystem Clock Oscillation 1, 2
4
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