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UPD75P0076CU View Datasheet(PDF) - NEC => Renesas Technology

Part Name
Description
Manufacturer
UPD75P0076CU
NEC
NEC => Renesas Technology NEC
UPD75P0076CU Datasheet PDF : 62 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
µPD75P0076
3.2 Non-port Pins (1/2)
Pin name I/O Alternate function
Function
TI0
I P13
Inputs external event pulses to the timer/event
TI1
P12/INT2
counter.
PTO0
O P20
Timer/event counter output
PTO1
P21
PCL
P22
Clock output
BUZ
P23
Optional frequency output (for buzzer output or
system clock trimming)
SCK
I/O P01
Serial clock I/O
SO/SB0
P02
Serial data output
Serial data bus I/O
SI/SB1
P03
Serial data input
Serial data bus I/O
INT4
I P00
Edge detection vectored interrupt input (both rising
edge and falling edge detection)
INT0
INT1
INT2
I P10
P11
P12/TI1
Edge detection vectored
interrupt input (detection
edge can be selected).
INT0/P10 can select a noise
eliminator.
Rising edge detection
testable input
Noise eliminator/
asynchronous selection
Asynchronous
Asynchronous
KR0 to KR3
I P60/AN4 to
P63/AN7
Falling edge detection testable input
AN0 to AN3
AN4 to AN7
I P110 to P113 Analog signal input
P60/KR0 to
P63/KR3
AVREF
A/D converter reference voltage
AVSS
A/D converter reference GND potential
X1
I
Crystal/ceramic connection pin for the main system
X2
clock oscillator. When inputting the external clock,
input the external clock to pin X1, and the inverted
phase of the external clock to pin X2.
XT1
I
Crystal connection pin for the subsystem clock
XT2
oscillator. When the external clock is used, input the
external clock to pin XT1, and the inverted phase of
the external clock to pin XT2. Pin XT1 can be used
as a 1-bit input (test) pin.
RESET
I
System reset input (low-level active)
Note Circuit types enclosed in brackets indicate Schmitt triggered inputs.
After
reset
Input
Input
Input
Input
Input
Input
Circuit
typeNote
<B>-C
E-B
<F>-A
<F>-B
<M>-C
<B>
<B>-C
<Y>-D
Y-A
<Y>-D
Z-N
Z-N
<B>
7

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