UPD75P3018AGK-9EU View Datasheet(PDF) - NEC => Renesas Technology
Part Name
Description
Manufacturer
UPD75P3018AGK-9EU Datasheet PDF : 64 Pages
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1. PIN CONFIGURATION (Top View)
• 80-pin plastic QFP (14 × 14 mm)
µPD75P3018AGC-3B9, 75P3018AGC-8BT
• 80-pin plastic TQFP (fine pitch) (12 × 12 mm)
µPD75P3018AGK-BE9, 75P3018AGK-9EU
µPD75P3018A
S12
S13
S14
S15
S16
S17
S18
S19
S20
S21
S22
S23
S24/BP0
S25/BP1
S26/BP2
S27/BP3
S28/BP4
S29/BP5
S30/BP6
S31/BP7
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
52
10
51
11
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P60/KR0
X2
X1
VPPNote
XT2
XT1
VDD
P33/MD3
P32/MD2
P31/SYNC/MD1
P30/LCDCL/MD0
P23/BUZ
P22/PCL/PTO2
P21/PTO1
P20/PTO0
P13/TI0
P12/INT2/TI1/TI2
P11/INT1
P10/INT0
P03/SI/SB1
Note Connect the VPP directly to VDD during normal operation.
PIN IDENTIFICATIONS
BIAS
: LCD Power Supply Bias Control
BP0-BP7
: Bit Port 0-7
BUZ
: Buzzer Clock
COM0-COM3 : Common Output 0-3
D0-D7
: Data Bus 0-7
INT0, 1, 4
: External Vectored Interrupt 0, 1, 4
INT2
: External Test Input 2
KR0-KR7
: Key Return 0-7
LCDCL
: LCD Clock
MD0-MD3
: Mode Selection 0-3
P00-P03
: Port0
P10-P13
: Port1
P20-P23
: Port2
P30-P33
: Port3
P40-P43
: Port4
P50-P53
: Port5
P60-P63
: Port6
P70-P73
PCL
PTO0-PTO2
RESET
S0-S31
SB0, SB1
SCK
SI
SO
SYNC
TI0-TI2
VDD
VLC0-VLC2
VPP
Vss
X1, X2
XT1, XT2
: Port7
: Programmable Clock
: Programmable Timer Output 0-2
: Reset
: Segment Output 0-31
: Serial Bus 0,1
: Serial Clock
: Serial Input
: Serial Output
: LCD Synchronization
: Timer Input 0-2
: Positive Power Supply
: LCD Power Supply 0-2
: Programming Power Supply
: Ground
: Main System Clock Oscillation 1, 2
: Subsystem Clock Oscillation 1, 2
4
Data Sheet U11917EJ2V0DS00
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