UPD7759C View Datasheet(PDF) - NEC => Renesas Technology
Part Name
Description
Manufacturer
UPD7759C Datasheet PDF : 18 Pages
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µPD7759
1.2 PIN FUNCTION FOR STAND ALONE MODE
Pin
52-pin
40-pin
(Abbre-
QFP
DIP
I/O
viation) Pin No. Pin No.
Function
I0
11
I1
12
I2
15
I3
16
I4
17
I5
18
I6
19
I7
21
AEN/WR
22
SAA
23
ALE
25
MD
34
ST
35
CS
38
A0
41
A1
42
A2
43
A3
44
A4
45
A5
47
A6
48
A7
49
A8
50
ASD0
51
ASD1
2
ASD2
3
ASD3
4
ASD4
5
ASD5
8
ASD6
9
ASD7
10
4
Message selection code input.
5
The message selection code signals are positive logics.
6
Ground the pins not used.
7
Input
These pins are connected to the internal latch circuit which
8
latches I0 to I7 data at the rising edge of the ST input.
9
In standby mode, these pins should be set high or low level.
10
If they are biased at or near the typical CMOS threshold,
11
the excess supply current is caused.
This signal is at low level while address signal is valid.
Output/
12
Controls the latch circuit for the higher 8 bits of the external
Input
ROM address.
Outputs high level when the start address of a message stored
13
Output
in the directory area of data memory, is being read out.
Determines the timing that higher 8 bits of the external ROM
15
Output address are externally latched. They must be latched at the
falling edge of the signal.
21
Input set at high-level.
Start signal input.
When ST goes low while CS is at low level, the µPD7759 starts
22
Input synthesizing the message specified by I0 to I7. In standby
mode, this signal resets the standby mode and starts speech
synthesis.
Chip select signal input.
25
Input
ST becomes valid when CS goes low.
26
27
28
29
30
Output Outputs the lower 9 bits of the external ROM address.
31
32
33
34
35
36
37
(1) Outputs the higher 8 bits of external ROM address.
38
Input/ (2) Inputs 8-bit speech synthesis data from the external ROM.
39
Output These functions are executed from (1) to (2) on a time-
1
shared basis.
2
3
4
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