UPD77113AF1-XXX-CN1 View Datasheet(PDF) - NEC => Renesas Technology

Part Name

Description

Manufacturer

UPD77113AF1-XXX-CN1

16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSORS

NEC => Renesas Technology 

µPD77113A, 77114

2.3 Data Memory Unit

The data memory unit consists of two banks of data memory and two data addressing units.

2.3.1 Data memory

The capacity and type of the memory differ depending on the model of the DSP. All DSPs have two banks of data

memory (X data memory and Y data memory). A 64-word peripheral area is assigned in the data memory space.

The µPD77113A and 77114 have 16K words × 2 banks data RAM and 32K words × 2 banks data ROM.

In addition, the µPD77114 has an external data memory interface so that the external memory can be expanded

to 8K words × 2 banks.

2.3.2 Data addressing unit

An independent data addressing unit is provided for each of the X data memory and Y data memory spaces.

Each data addressing unit has four data pointers (DPn), four index registers (DNn), one modulo register (DMX or

DMY), and an address ALU.

2.4 Peripheral Units

A serial interface, host interface, general-purpose I/O port, and wait cycle register are provided. All these internal

peripherals are mapped to the X data memory and Y data memory spaces, and are accessed from program as

memory-mapped I/Os.

2.4.1 Serial interface (SIO)

Two serial interfaces are provided. These serial interfaces have the following features:

• Serial clock : Supplied from external source to each interface. The same clock is used for input and output

on the interface.

• Frame length: 8 or 16 bits, and MSB or LSB first selectable for each interface and input or output

• Handshake : Handshaking with external devices is implemented with a dedicated status signal. With the

internal units, polling, wait, or interrupt are used.

2.4.2 Host interface (HIO)

This is an 8-bit parallel port that inputs data from or outputs data to an external host CPU or DMA controller. In

the DSP, a 16-bit register is mapped to memory for input data, output data, and status. Handshaking with an external

device is implemented by using a dedicated status signal. Handshaking with internal units is achieved by means of

polling, wait, or interrupts.

2.4.3 General-purpose I/O port (PIO)

This is a 4-bit I/O port that can be set in the input or output mode in 1-bit units.

2.4.4 Wait cycle register

The number of wait cycles to be inserted when the external data memory area is accessed can be specified in

advance by using a register (DWTR)Note. The number of wait cycles that can be set is 1, 3, or 7.

Note This function is not available on the µPD77113A because this DSP does not have an external data area.

Data Sheet U14373EJ3V0DS

19

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