UPD77210 View Datasheet(PDF) - NEC => Renesas Technology

Part Name

Description

Manufacturer

UPD77210

16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR

NEC => Renesas Technology 

µPD77210, 77213

5.2.2 Host reboot

The instruction code is obtained via the host interface and transferred to the instruction RAM.

The entry address is 0x5. Host rebooting is executed by setting the following parameters and then calling this

address.

• R7L: Number of instruction steps to be rebooted

• R6L: Host status register (HST)

• DP2: Transfer destination address of instruction to be rebooted (offset 0x8000 in the case of internal instruction

RAM area)

• R5L: Transfer destination data page register (DPR) (Specify 0x80 of the internal instruction RAM area.)

5.2.3 Serial reboot

The instruction code is obtained via the serial interface (TDMSIO) and then transferred to the instruction RAM.

The entry address is 0x6. Host rebooting is executed by setting the following parameters and then calling this

address.

• R7L: Number of instruction steps to be rebooted

• R6L: Serial status register (SST) (Specify 0x0EC0.)

• DP2: Transfer destination address of instruction to be rebooted (offset 0x8000 in the case of internal instruction

RAM area)

• R5L: Transfer destination data page register (DPR) (Specify 0x80 of the internal instruction RAM area.)

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Data Sheet U15203EJ3V0DS

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