VORTEX86SX View Datasheet(PDF) - Unspecified

Part Name

Description

Manufacturer

VORTEX86SX

32-BIT x86 Embedded SoC

Unspecified 

Vortex86SX

32-Bit x86 Embedded SoC

4.2

Signal Description

This chapter provides a detailed description of Vortex86SX signals. A signal with the symbol ”_n” at the end of itself indicates

that this pin is low active. Otherwise, it is high active.

The following notations are used to describe the signal types:

I

Input pin

O

Output pin

OD

Output pin with open-drain

I/O

Bi-directional Input/Output pin

z System (7 PINs)

PIN No.

Symbol

AA26

PWRGOOD

AB26

Y26

Y25

AA25

AB25

Y23

25MOUT

XOUT_14.318

XIN_14.318

MTBF

CLK24MOUT

SPEAKER

Type

Description

Power-Good Input. This signal comes from Power Good of the power supply

I to indicate that the power is available. The Vortex86SX uses this signal to

generate reset sequence for the system.

O 25MHz Clock output.

O Crystal-out. Frequency output from the inverting amplifier (oscillator).

I

Crystal-in. 14.318MHz frequency input, within 100 ppm tolerance, to the

amplifier (oscillator).

MTBF Flag output.

O 24MHz Clock output

O

Speaker Output. This pin is used to control the Speaker Output and should

be connected to the Speaker

z SDRAM /DDRII Interface (44 PINs)

PIN No.

B9

A9

D13

E12

C13

B13, E13

Symbol

SDRAMCLK

SDRAMCLKN

RAS_

CAS_

WE_

CS_[1:0]

Type

Description

O

Clock output. This pin provides the fundamental timing for the SDRAM /DDR

controller.

O

Clock output. This pin provides the fundamental timing for the SDRAM /DDR

controller.

Row Address Strobe. When asserted, this signal latches row address on

O positive edge of the SDRAM/DDR clock. This signal also allows row access

and pre-charge.

Column Address Strobe. When asserted, this signal latches column address

O on the positive edge of the SDRAM/DDR clock. This signal also allows

column access and pre-charge.

O

Memory Write Enable. This pin is used as a write enable for the memory

data bus.

Chip Select CS[1:0]. These two pins activate the SDRAM devices. First Bank

of SDRAM accepts any command when the CS0_n pin is active low. Second

O Bank of SDRAM accepts any command when the CS1_n pin is active low.

B14, D17

E16, D14

DQM[1:0]

DQS[1:0]

For DDRII, only CS0_n activates the DDR device.

O

Data Mask DQM[1:0]. These pins act as synchronized output enables during

read cycles and byte masks during write cycles.

I/O

Data Strobe DQS[1:0 for DDR only. Output with write data, input with the

read data for source synchronous operation.

Vortex86SX Brief Datasheet

7

Version 1.001

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