VSC7139TW View Datasheet(PDF) - Vitesse Semiconductor

Part Name

Description

Manufacturer

VSC7139TW

Quad Transceiver for Gigabit Ethernet and Fibre Channel

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Quad Transceiver for

Gigabit Ethernet and Fibre Channel

Preliminary Datasheet

VSC7139

Table 7: Pin Identifications

Pin

Name

Description

N1, N2, N3

N4, M1, M2, M3,

M4, L1

L2

J1, J2, J3

J4, H1, H2

H3, H4, G1

G2

G16, G15, G14

H17, H16, H15

H14, J17, J16 J15

L17, L16, L15

L14, M17, M16

M15, M14, N17

N16

R2

P3

R1

P2

P16

P14

K1, F1

K17, P17

P1

TA0, TA1, TA2

TA3, TA4, TA5

TA6, TA7, TA8

TA9

TB0, TB1, TB2

TB3, TB4, TB5

TB6, TB7, TB8

TB9

TC0, TC1, TC2

TC3, TC4, TC5

TC6, TC7, TC8

TC9

TD0, TD1, TD2

TD3, TD4, TD5

TD6, TD7, TD8

TD9

REF+

REF-

REFT

RFCM

RFCO0

RFCO1

TBCA, TBCB

TBCC, TBCD

LTCN

INPUT - TTL: 10-bit Transmit bus for Channel A. Parallel data on this bus is latched on

the rising edge of REF, TBCC or TBCA. TA0 is transmitted first.

INPUT - TTL: 10-bit Transmit bus for Channel B. Parallel data on this bus is latched on

the rising edge of REF, TBCC or TBCB. TB0 is transmitted first.

INPUT - TTL: 10-bit Transmit bus for Channel C. Parallel data on this bus is latched on

the rising edge of REF or TBCC. TC0 is transmitted first.

INPUT - TTL: 10-bit Transmit bus for Channel D. Parallel data on this bus is latched on

the rising edge of REF, TBCC or TBCD. TD0 is transmitted first.

INPUT - Differential PECL or TTL: This rising edge of REF+/- provides the reference

clock, at 1/10th or 1/20th of the baud rate (depending on RFCM) to the Clock

Multiplying PLL. If REF+/- is used, either leave REFT open or set REFT HIGH.

Internally biased to VDD/2. If all TBCx inputs are HIGH, the rising edge of REF will

latch Tx(0:9) on all four channels

INPUT - TTL: TTL REFerence clock. This rising edge of REFT provides the reference

clock, at 1/10th or 1/20th of the baud rate (depending on RFCM) to the Clock

Multiplying PLL. If REFT is used, set REF+ HIGH and leave REF- open. If all TBCx

inputs are HIGH, the rising edge of REFT will latch Tx(0:9) on all four channels

INPUT - TTL: REFerence clock Mode select. When LOW, REF is at 1/20th of the

transmit baud rate (i.e. 62.5 MHz for 1.25 Gb/s). When HIGH, REF is at 1/10th the baud

rate (i.e. 125 MHz for 1.25 Gb/s).

OUTPUT - TTL: These are identical copies of the transmit baud rate clock divided by 10.

INPUT - TTL: Per channel Transmit Byte Clock for Channel x. All four channels’

parallel Tx(0:9) inputs may be timed to REF, TBCC, or independently to TBCx. Refer to

the Serializer description.

INPUT - TTL: Latch Transmit Byte Clocks. When LOW, internal PLLs align clocks with

each of the transmit byte clocks, if present. Data may be corrupted when LOW. When

HIGH, alignment will remain static regardless of actual TBCx location.

Page 12

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

G52196-0, Rev 3.3

5/14/01

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