VSC8114 View Datasheet(PDF) - Vitesse Semiconductor
Part Name
Description
Manufacturer
VSC8114
Vitesse Semiconductor
VSC8114 Datasheet PDF : 24 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux
with Integrated Clock Generation and Clock Recovery
Data Sheet
VSC8114
PECL input LOSPECL to force the part into a Loss of Signal state. Most optics have a PECL output usually
called “SD” or “FLAG” indicating the presence or lack of optical power. Depending on the optics manufacturer
this signal is either active high or active low. The LOSTTL and LOSPECL inputs are XNOR’d to generate an
internal LOS control signal. See Figure 2. The optics “SD” output should be connected to LOSPECL. The
LOSTTL input should be tied to low if the optics “SD” is active high. If it’s active low tie LOSTTL to a high.
The inverse is true if the optics use “FLAG” for loss of signal
Figure 2: Data and Clock Receive Block Diagram
VSC8114
PM5355
LOSPECL
LOSTTL
LOSDETEN_
DQ
DQ
RXOUT[7:0]
DQ
DSBLCRU
RXDATAIN+/-
RXCLKIN+/-
Losdet
CRU
1
0
0
0
1
1
DQ
Divide-by-8
FP
RXLSCKOUT
DQ
CMU
Facility Loopback
The Facility Loopback function is controlled by the FACLOOP signal. When the FACLOOP signal is set
high, the Facility Loopback mode is activated and the high speed serial receive data (RXDATAIN) is presented
to the high speed transmit output (TXDATAOUT). See Figure 3. In Facility Loopback mode the high speed
receive data (RXDATAIN) is also converted to parallel data and presented to the low speed receive data output
pins (RXOUT[7:0]). The receive clock (RXCLKIN) is also divided down and presented to the low speed clock
output (RXLSCKOUT).
Figure 3: Facility Loopback Data Path
RXDATAIN
RXCLKIN
TXDATAOUT
FACLOOP
CRU
DQ
Recovered
Clock
0
1
1
QD
0
1
0
1:8
Serial to
Parallel
DQ
8:1
Parallel to
Serial
QD
PLL
RXOUT[7:0]
TXIN[7:0]
Page 4
© VITESSE SEMICONDUCTOR CORPORATION
G52185-0, Rev 4.0
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
11/1/99
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