VSC8116QP1 View Datasheet(PDF) - Vitesse Semiconductor

Part Name

Description

Manufacturer

VSC8116QP1

ATM/SONET/SDH 622/155Mb/s Transceiver Mux/Demux with Integrated Clock Generation

Vitesse Semiconductor 

Data Sheet

VSC8116

VITESSE

SEMICONDUCTOR CORPORATION

ATM/SONET/SDH 622/155Mb/s Transceiver

Mux/Demux with Integrated Clock Generation

Figure 4: Equipment Loopback Data Path

RXDATAIN

RXCLKIN

TXDATAOUT

EQULOOP

DQ

QD

0

1:8

Serial to

1

Parallel

0

÷8

1

8:1

Parallel to

Serial

DQ

QD

PLL

÷8

RXOUT[7:0]

RXLSCKOUT

TXIN[7:0]

TXLSCKOUT

Split Loopback

Equipment and facility loopback modes can be enabled simultaneously. See descriptions for equipment and

facility loop modes above. The only change is, since they are both active, RXDATAIN will not be deserialized

and presented to RXOUT[0:7], and TXIN[0:7] will not be serialized and present to TXDATAOUT.

Figure 5: Split Loopback Datapath

RXDATAIN

RXCLKIN

TXDATAOUT

FACLOOP

DQ

1

QD

0

1

0

0

1:8

Serial to

Parallel

1

0

÷8

1

8:1

Parallel to

Serial

PLL

DQ

QD

RXOUT[7:0]

RXLSCKOUT

TXIN[7:0]

EQULOOP

Loop Timing

LOOPTIM0 mode bypasses the CMU when the LOOPTIM0 input is asserted high. In this mode the CMU

is bypassed by using the receive clock (RXCLKIN), and the entire part is synchronously clocked from a single

external source.

G52220-0, Rev 4.1

1/8/00

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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