VSC8150QQ View Datasheet(PDF) - Vitesse Semiconductor
Part Name
Description
Manufacturer
VSC8150QQ Datasheet PDF : 20 Pages
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2.488Gb/s SONET/SDH
Overhead Monitor
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Data Sheet
VSC8150
Table 2: SONET/SDH Rate Select Settings
Function
STS-3/STM-1
STS-12/STM-4
STS-48/STM-16
Invalid
RATESEL1
0
1
0
1
RATESEL0
1
0
0
1
Descrambler
Framed SONET/SDH bytes are descrambled using a frame synchronous descrambler with generating poly-
nomial 1 + X6 + X7 and a sequence length of 127. The scrambling algorithm is reset to an all 1's state immedi-
ately following the Z0 byte ((SONET 192 x 3) | (SDH 64x9) = 577th received byte in frame). All A1, A2, and
J0/Z0 bytes are not descrambled (R5-6).
B1 Error Monitoring
The section bit-interleaved parity (BIP-8) error detection code B1 will be calculated for every frame before
de-scrambling and compared to its extracted value after de-scrambling the B1 value in the following frame (R3-
16). If B1 errors were detected in the previous frame a series of pulses will appear on the B1ERR output, begin-
ning approximately 60ns after the B1 byte is received. The number of pulses indicates the quantity of errored
bit positions detected; the absence of pulses indicates no received B1 errors, and eight pulses would indicate the
maximum number of received B1 errors. The pulses are eight parallel clocks wide (25.7nS at 2.488GHz RXS-
CLKIN), and spaced apart by the same amount (See figure 10).
Overhead Byte Read Out
Overhead bytes are descrambled (with the exception of A1, A2, and J0) and output from SOHOUT[7:0] in
the order of their appearance in the frame. Only the bytes from the first STS-1 frame or the first, fourth, and
seventh columns of the first STM-1 frame are presented (See Figure 6). Accompanying the data from the
SOHOUT[7:0] output are the output clock SOHCLK and frame pulse RXFPOUT (See Figures 8 and 9).
The SOHOUT output is undefined when SEF is high. The user should be aware that overhead data from
one frame prior to the RXFRERR pulse could be corrupted and should not be used for OAM&P functions.
FPGA Interface
RXFPOUT is used to provide a reference point to the 27 byte sequence of overhead bytes and clocks. It is
suggested that the SOHCLK be used to clock an external counter with RXFPOUT used as the counter reset.
The count value can be used as the overhead byte address, and RXPOUT will reset the counter when it reaches
a logical value of 27. The high order bit of this counter is useful for indicating when the B1 pulse train results
can be read. A block diagram illustrates this arrangement more clearly. (See Figure 3).
Page 4
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52186-0, Rev. 3.0
10/12/98
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