VT82C42 View Datasheet(PDF) - Unspecified
Part Name
Description
Manufacturer
VT82C42 Datasheet PDF : 13 Pages
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VIA Technologies, Inc.
VT82C42
6. VT82C42 Signal Description
Table 4. Signal Description for VT82C42
Symbol
D -D
07
(BUS)
P -P
10 13
40-Pin
12-19
27-30
P -P
20 27
P14-P15
21-24
35-38
31, 32
P16-P17
WR#
RD#
CS#
A0
TEST 0,
TEST 1
XTAL 1,
XTAL 2
TH_SS
TH_PROG
TH_SSPP
TL_EA
SYNC
NC
RESET#
VCC
GND
33, 34
10
8
6
9
1
39
2
3
5
25
26
7
11
4
40
20
44-Pin
14-20
Type
Name and Function
I/O Act as data input or data output.
30-33
24-27
39-42
35, 36
37, 38
11
9
7
10
2
43
3
4
6
28
29
8
12
1, 13, 23,
34
5
44
22
I/O Pullup open drain port. Writing a '1' to these ports tri-states the
ports. Act as input 'high' simultaneously if no outside 'low'
connection. Writing a '0' to these ports results in generating a low
on the port.
Output Port 20 - Output Port 23
O Output Port 24 - Output Port 27
I/O Pullup open drain port. Writing a '1' to these ports tri-states the
ports. Act as input 'high' simultaneously if no outside 'low'
connection. Writing a '0' to these ports results in generating a low
on the port.
I Input port 16, Input port 17
I Act as a write signal.
I Act as a read signal.
I Chip select of this chip.
I Command/Data select when RD# or WR# is active.
I Act as Keyboard clock input in both AT mode & PS2 mode
Act as Keyboard Data input in AT mode. Act as Mouse Clock
input in PS2 mode.
I Act as clock input to the chips. Can be connected to LC circuit or
a single clock source (X2).
I Tie to VCC
I Tie to ground.
O Internal state synchronous output.
I No connection.
I A low in this pin reset the chip to a known state.
Power supply of 4.5 to 5.5v.
Ground.
1. Description for Table 4
RESET# is active low and is only an input pin. VT82C42 requires 10 clocks before RESET# goes to high to
have the chip go to a known state.
Pins WR#, RD#, CS# and Ao are all input only pins and must activate for at least one clock cycle width to be
recognised by the VT82C42.
D0-d7 are two-way pins, each having 4mA TTL compatible output driving. When D0-D7 is provided by the
host, write cycle data should cover all the WR# CS# A0 command width. When the D0-D7 is provided by the
VT82C42, the D0-D7 is available as long as the RD#=0 CS#=0 command is asserted and is held one clock
cycle after the command is deasserted.
TEST0,TEST1 are input only pins. TEST0 is expected to connect to KBCLK no matter what mode the
VT82C42 is in. TEST1 is expected to connect to KBDATA when in AT-mode, and is expected to connect to
MSCLK when in PS/2 mode. They have a 50K ohm pull up internally.
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