W83194BR-323 View Datasheet(PDF) - Winbond
Part Name
Description
Manufacturer
W83194BR-323 Datasheet PDF : 18 Pages
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W83194BR-323W83194BG-323
STEPLESS CLOCK FOR INTEL BROOKDALE CHIPSET
7. I2C CONTROL AND STATUS REGISTERS
7.1 Register 0: Frequency Select Register (default = 0)
BIT
NAME
PWD
DESCRIPTION
7 EN_SPSP
Enable Spread Spectrum in the frequency table.
0 0 = Normal 1 = Spread Spectrum enabled
6 SSEL [4]
0
5 SSEL [3]
4 SSEL [2]
0
0 Frequency selection by software via I2C.
3 SSEL [1]
0
2 SSEL [0]
0
Enable software program FS [4:0].
1 EN_SSEL
0 0 = Select frequency by hardware.
1= Select frequency by software I2C - Bit 6 ~ 2.
Enable reload safe frequency when the watchdog is timeout.
0 EN_SAFE_FREQ 0 0 = reload the FS [4:0] latched pins when watchdog time out.
1 = reload the safe frequency bit defined at Register 5 bit 4~0.
7.2 Register 1: CPU Clock Register (1 = enable, 0 = Stopped)
BIT
PIN NO
7 44,45
6 37,38
5 40,41
4-
3-
2-
1-
0-
PWD
1 CPUCLK_T2 / C2
1 CPUCLK_T1 / C1
1 CPUCLK_T0 / C0
X FS [4] Read back.
X FS [3] Read back
X FS [2] Read back
X FS [1] Read back
X FS [0] Read back
DESCRIPTION
7.3 Register 2: PCI Clock Register (1 = enable, 0 = Stopped)
BIT
PIN NO
7 48
6 17
5 16
4 15
3 14
2 12
1 11
0 10
PWD
DESCRIPTION
X MULTISEL0 trapping pin data read back
1 PCICLK6
1 PCICLK5
1 PCICLK4
1 PCICLK3
1 PCICLK2
1 PCICLK1
1 PCICLK0
Publication Release Date: March 2006
-7-
Revision 2.1
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