W83626D View Datasheet(PDF) - Winbond

Part Name

Description

Manufacturer

W83626D

LPC TO ISA BRIDGE SET

Winbond 

W83626F/W83626D/W83626G

ISA Interface Signals, continued

SYMBOL

PIN

OWS#

81

LA[23:17]

103-104

106-109

111

SMEMW#

82

SMEMR#

83

REFRESH#

91

BALE

101

SBHE#

102

MEMR#

112

MEMW#

113

MASTER#

123

RTCEN#

IRQ3

98

IRQ4

97

I/O

INt

I/O24t

OUT24

OUT24

OUT24

OUT24

OUT24

I/O24t

I/O24t

INt

INt

INt

FUNCTION

Zero Wait States. An ISA slave asserts ZEROWS# after

its address and command signals have been decoded to

indicate that the current cycle can be executed as an ISA

zero wait state cycle. ZEROWS# has no effect during 16-bit

I/O cycles.

Unlatched Address. The LA [23:17] address lines are

bi-directional. These address lines allow accesses to

physical memory on the ISA Bus up to 16 Mbytes. LA

[23:17] are outputs when the W83628F owns the ISA Bus.

Standard Memory Write. SMEMW# asserted indicates

the current ISA bus cycle is a memory write cycle to an

address below 1 Mbyte.

Standard Memory Read. SMEMR# asserted indicates the

current ISA bus cycle is a memory read cycle to an address

below 1 Mbyte.

Refresh. REFRESH# asserted indicates that a refresh

cycle is in progress, or that an ISA master is requesting

W83626F/G to generate a refresh cycle. Upon PCIRST#,

this signal is tri-stated.

Bus Address Latch Enable. BALE is an active high signal

asserted by the W83626F/G to indicate that the address

(SA [19:0], LA [23:17]) and SBHE# signal lines are valid.

The LA [23:17] address lines are latched on the trailing

edge of BALE. BALE remains asserted throughout DMA

and ISA master cycles. BALE is driven low upon PCIRST#.

System Byte High Enable. SBHE# asserted indicates that

a byte is being transferred on the upper byte (SD [15:8]) of

the data bus. SBHE# is at an unknown state upon

PCIRST#.

Memory Read. MEMR# asserted indicates the current ISA

bus cycle is a memory read.

Memory Write. MEMW# asserted indicates the current

ISA bus cycle is a memory write.

MASTER#. This signal is used with a DREQ line by an ISA

master to gain control of the ISA Bus.

RTC Function Enable. The pin applies a pull-down resistor

(4.7K ohm) to enable RTC functions ( RTCCS#, and IRQ8)

Parallel Interrupt Requested Input 3.

Parallel Interrupt Requested Input 4.

Publication Release Date: May 25, 2005

-7-

Revision A1

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