WCMC1616V9X View Datasheet(PDF) - Weida Semiconductor, Inc.
Part Name
Description
Manufacturer
WCMC1616V9X Datasheet PDF : 13 Pages
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ADVANCE INFORMATION
WCMC1616V9X
Switching Characteristics (Over the Operating Range)[11]
Parameter
Read Cycle
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tDBE
tLZBE
tHZBE
tSK
Write Cycle[13]
tWC
tSCE
tA W
tH A
tSA
tPWE
tB W
tS D
tHD
tHZWE
tLZWE
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW and CE2 HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z[12, 14]
OE HIGH to High Z[12, 14]
CE LOW and CE2 HIGH to Low Z[12, 14]
CE HIGH and CE 2 LOW to High Z[12, 14]
BLE /BHE LOW to Data Valid
BLE/BHE LOW to Low Z[12, 14]
BLE/BHE HIGH to High-Z[12, 14]
Address Skew
Write Cycle Time
CE LOW and CE2 HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z[12, 14]
WE HIGH to Low Z[12, 14]
WCMC1616V9X-70
Min.
Max.
Unit
70
ns
70
ns
10
ns
70
ns
35
ns
5
ns
25
ns
5
ns
25
ns
70
ns
5
ns
25
ns
10
ns
70
ns
55
ns
55
ns
0
ns
0
ns
55
ns
55
ns
25
ns
0
ns
25
ns
5
ns
Notes:
11. Test conditions assume signal transition time of 1V/ns or higher , timing reference levels of V CC(typ)/2, input pulse levels of 0V to VCC(typ), and output loading
of the specified IOL/IOH and 30-pF load cpacitance
12. tHZOE, t HZCE, t HZBE and t HZWE transitions are measured when the outputs enter a high-impedance state.
13. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE =VIL. All signals must be ACTIVE to initiate a write and any
of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates
the write
14. High-Z and Low-Z parameters are characterized and are not 100% tested.
Document #: 38-14027 Rev. **
Page 6 of 13
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