WPCN384U View Datasheet(PDF) - Winbond
Part Name
Description
Manufacturer
WPCN384U Datasheet PDF : 3 Pages
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Features
■ Two Serial Ports (SP1 and SP2)
— Software compatible with the 16550A and the 16450
— Shadow register support for write-only bit monitoring
— UART data rates up to 1.5 Mbaud
■ IEEE 1284-Compliant Parallel Port
— ECP, with Level 2 (14 mA sink and source output
buffers)
— Software or hardware control
— Enhanced Parallel Port (EPP) compatible with EPP
1.7 and EPP 1.9
— Supports EPP as mode 4 of the Extended Control
Register (ECR)
— Selection of internal pull-up or pull-down resistor for
Paper End (PE) pin
— Supports a demand DMA mode mechanism and a
DMA fairness mechanism for improved bus utilization
— Protection circuit that prevents damage to the
parallel port when a printer connected to it is pow-
ered up or is operated at high voltages (in both
cases, even if the WPCN384U is in power-down
state)
■ 21 General-Purpose I/O (GPIO) Ports
— Supports IRQ assertion
— Programmable drive type for each output pin (open-
drain, push-pull or output disable)
— Programmable option for internal pull-up resistor on
each input pin
— Output lock option
— Input debounce mechanism
■ LPC System Interface
— 8-bit I/O cycles
— LPCPD and CLKRUN support
— Implements PCI mobile design guide recommenda-
tion (PCI Mobile Design Guide 1.1, Dec. 18, 1998)
■ PC2001 and ACPI 3.0 Compliant
— PnP Configuration Register structure
— Flexible resource allocation for all logical devices
❏ Relocatable base address
❏ 15 IRQ routing options
❏ Optional 8-bit DMA channels (where applicable)
selected from four possible DMA channels
■ Clock Sources
— 14.318 MHz or 48 MHz clock input
— LPC clock, 0 or 30 MHz to 33 MHz
■ Strap Configuration
— Base Address (BADDR) strap to determine the base
address of the Index-Data register pair
— Strap Inputs to select testability mode
■ Power Supply
— 3.3V supply operation
— All pins are 5V tolerant, except LPC bus pins
— All pins are back-drive protected, except LPC bus pins
■ Testability
— XOR Tree
— TRI-STATE device pins
Internal Block Diagram
14.31818 MHz
Clock
Generator
Parallel Port Interface
IEEE 1284
Parallel Port
LPC Interface
Bus
Interface
48 MHz
GPIO Ports
Serial Port
Serial Port
Ports
I/O
Serial
Interface
Serial
Interface
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Revision 1.0
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