WPC8768L View Datasheet(PDF) - Winbond

Part Name

Description

Manufacturer

WPC8768L

Mobile Embedded Controller with SPI™ Flash Interface and MCE-Compliant CIR Port

Winbond 

Device-Specific Information

The following table shows the main differences between the WPC8768L and WPC8769L devices.

Feature

FIR Port

WPC8768L

✔

WPC8769L

✘

Features

Embedded Controller Features

■ Processing Unit

— CompactRISC CR16CPlus 16-bit embedded RISC

processor core (the “core”)

— Up to 4 Mbytes of external address space

■ Internal Memory

— 1 Kbyte of ROM

— 4 Kbytes of on-chip RAM

— All memory types can hold both code and data

■ Flash Interface Unit (FIU)

— Up to 4 Mbytes of code and data

— Hardware-protected boot zone block protection

— SPI External Memory

❏ Up to 32 Mbits

❏ Fast Read mode

❏ Page programing support

❏ Configurable clock rate

— Field upgradeable

■ Shared Memory Controller (SHM)

— Supports BIOS (flash) memory sharing with PC host

— Supports host-controlled code download and update

— Memory access protection

LPC System Interface

■ Based on Intel’s LPC Interface Specification Revision

1.1, August 2002

■ Four optional 8-bit DMA channels

■ I/O, Memory and 8-bit Firmware Memory read and write

cycles, Firmware Memory writes may insert wait cycles

■ Bootable Memory Support

■ Base Address (BADDR1-0) straps to determine the

base address of the index-data register pair

— Alternate base address configurable by the core

■ LPCPD and CLKRUN support

Embedded Controller System Features

■ Host Interface

— Comprises host interface channels, typically used

for KBC and ACPI Private or Shared EC channels

— 8042 KBC-standard interface (legacy 60h, 64h)

— Two PM interface ports (legacy 62h, 66h; 68h, 6Ch)

— ACPI EC with either Shared or Private interface

through the PM interface

— Two Mailbox areas for host-core communication, up

to 4 Kbytes each; maximum 4 Kbytes total

— Generates IRQ, SMI and SCI

— Provides IRQ1 and IRQ12 support

— Provides Fast Gate A20 and Fast Host reset via firmware

■ Interrupt Control Unit (ICU)

— 31 maskable vectored interrupts (of which eight are

external)

— General-purpose external interrupt inputs through

MIWU

— Enable and pending indication for each interrupt

— Non-maskable interrupt input

■ Multi-Input Wake-Up (MIWU)

— Up to 40 wake-up or interrupt inputs

— Generates wake-up event to PMC (Power Manage-

ment Controller)

— Generates interrupts to ICU

— User-selectable trigger conditions

■ Internal Keyboard Matrix Scanning

— Up to 18 open-collector outputs (at least 12)

— Eight Schmitt inputs with internal pull-ups

■ General-Purpose I/O (GPIO) Ports

— 64 port pins

— I/O pins individually configured as input or output

— Configurable internal pull-up / pull-down resistors

— Outputs individually configured as push-pull or

open-drain

— Two echo inputs with wake-enabled interrupts

— Additional 12 GPIOs with wake-enabled interrupts

— Four GPIOs capable of 12 mA sink current

— Seven GPIOs are accessible to the host

— Optional low-cost external GPIO expansion through

the SensorPath interface

■ PS/2 Interface

— Three external ports: can be used for keyboard,

mouse and an additional pointing device

— Byte-level handling via hardware accelerator

www.winbond.com

2

Revision 1.0

Share Link: