EL5283CY View Datasheet(PDF) - Elantec -> Intersil
Part Name
Description
Manufacturer
EL5283CY Datasheet PDF : 9 Pages
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EL5283C - Preliminary
Dual and Window 8ns High-Speed Comparators
Pin Descriptions
Pin Number
1
2
Pin Name
VS+
VREFH
Function
Positive supply voltage
Upper voltage reference
Equivalent Circuit
VS+
VREF
IN
3
IN
Input
4
VREFL
Lower voltage reference
5
VS-
Negative supply voltage
6
GDN
Digital ground
7
OUTL
Low output
8
LATCH
Latch
9
OUTH
High output
10
VSD
Digital supply voltage
Applications Information
Power Supplies and Circuit Layout
The EL5283C comparator operates with single and dual
supply with 5V to 12V between VS+ and VS-. The out-
put side of the comparators is supplied by a single
supply from 2.7V to 5V. The rail to rail output swing
enables direct connection of the comparator to both
CMOS and TTL logic circuits. As with many high speed
devices, the supplies must be well bypassed. Elantec rec-
ommends a 4.7µF tantalum in parallel with a 0.1µF
ceramic. These should be placed as close as possible to
the supply pins. Keep all leads short to reduce stray
capacitance and lead inductance. This will also mini-
mize unwanted parasitic feedback around the
comparator. The device should be soldered directly to
the PC board instead of using a socket. Use a PC board
with a good, unbroken low inductance ground plane.
Good ground plane construction techniques enhance sta-
bility of the comparators.
VS-
Circuit 4
(Reference Circuit 4)
(Reference Circuit 4)
(Reference Circuit 2)
(Reference Circuit 3)
(Reference Circuit 2)
Input Voltage Considerations
The EL5283C input range is specified from 0.1V below
VS- to 2.25V below VS+. The criterion for the input
limit is that the output still responds correctly to a small
differential input signal. The differential input stage is a
pair of PNP transistors, therefore, the input bias current
flows out of the device. When either input signal falls
below the negative input voltage limit, the parasitic PN
junction formed by the substrate and the base of the PNP
will turn on, resulting in a significant increase of input
bias current. If one of the inputs goes above the positive
input voltage limit, the output will still maintain the cor-
rect logic level as long as the other input stays within the
input range. However, the propagation delay will
increase. When both inputs are outside the input voltage
range, the output becomes unpredictable. Large differ-
ential voltages greater than the supply voltage should be
avoided to prevent damages to the input stage. Inputs of
unused channels should not be left floating. They should
be driven to a known state. For example, one input can
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