CXD2043Q View Datasheet(PDF) - Sony Semiconductor
Part Name
Description
Manufacturer
CXD2043Q Datasheet PDF : 11 Pages
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Pin Configuration
CXD2043Q
DVSS 65
DVDD 66
TEST 67
TEST 68
TEST 69
BPF 70
VI8 71
VI7 72
VI6 73
VI5 74
VI4 75
VI3 76
VI2 77
VI1 78
ADCO 79
INSL 80
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
40 CVDD
39 CVG
38 CVRF
37 CIRF
36 VB
35 YIRF
34 YVRF
33 YVG
32 YVDD
31 AYO
30 YVSS
29 RT
28 AAVD
27 ADIN
26 AAVS
25 RB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Pin Description
Pin
No.
Symbol
I/O
1 OCLK
I
2 DVSS
—
3 DVDD
—
4 CLKO O
5 MCK
I
6 ADCK
I
7 CK4
O
8 TEST
I
9 FIN
I
10 CPO
O
11 PVSS
—
Description
Clock amplifier input.
Input at 0.8Vp-p or more by eliminating DC components with a capacitor.
Digital ground
Digital power supply
Clock amplifier output.
Left open when the clock amplifier is not used.
Master clock input
Clock input for A/D converter. Input the same clock signal as for Pin 5.
4FSC clock output. Generated from the built-in 4-PLL.
Test. Fix to Low.
FSC clock input. Input FSC which is burst-locked.
Connect to DVss when the PLL is not used.
Phase comparison output for the built-in PLL.
Left open when the PLL is not used.
PLL analog ground
–2–
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