ADV7175 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADV7175 Datasheet PDF : 36 Pages
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ADV7175/ADV7176
MR27
MR26
MR25
MR24
MR23
MR22
MR21
MR20
RGB/YUV
CONTROL
MR26
0 RGB OUTPUT
1 YUV OUTPUT
CHROMINANCE
CONTROL
MR24
0 ENABLE COLOR
1 DISABLE COLOR
GENLOCK SELECTION
MR22 MR21
x 0 DISABLE GENLOCK
0 1 ENABLE SUBCARRIER
RESET PIN
1 1 ENABLE RTC PIN
LOWER POWER
MODE
MR27
0
DISABLE
1
ENABLE
BURST
CONTROL
MR25
0 ENABLE BURST
1 DISABLE BURST
CCIR624/CCIR601
CONTROL
MR23
0 CCIR624 OUTPUT
1 CCIR601 OUTPUT
SQUARE PIXEL
CONTROL
MR20
0
DISABLE
1
ENABLE
Figure 38. Mode Register 2
CCIR624/CCIR601 Control (MR23)
This bit switches the video output between CCIR624 and
CCIR601 video standard.
Chrominance Control (MR24)
This bit enables the color information to be switched on and off
the video output.
Burst Control (MR25)
This bit enables the burst information to be switched on and off
the video output.
RGB/YUV Control (MR26)
This bit enables the output from the RGB DACs to be set to
YUV output video standard. Bit MR06 of Mode Register 0
must be set to Logic Level “1” before MR26 is set.
Lower Power Control (MR27)
This bit enables the lower power mode of the ADV7175/
ADV7176.
NTSC PEDESTAL CONTROL REGISTERS 3–0
(PCE15–0, PCO15–0)
(Subaddress (SR4–SR0) = 11-0EH)
These 8-bit wide registers are used to set up the NTSC pedestal
on a line by line basis in the vertical blanking interval for both
odd and even fields. Figure 39 shows the four control registers.
A Logic “1” in any of the bits of these registers has the effect of
turning the pedestal off on the equivalent line.
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
FIELD 1/3 PCO7 PCO6 PCO5 PCO4 PCO3 PCO2 PCO1 PCO0
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 1/3 PCO15 PCO14 PCO13 PCO12 PCO11 PCO10 PCO9 PCO8
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
FIELD 2/4 PCE7 PCE6 PCE5 PCE4 PCE3 PCE2 PCE1 PCE0
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 2/4 PCE15 PCE14 PCE13 PCE12 PCE11 PCE10 PCE9 PCE8
Figure 39. Pedestal Control Registers
MODE REGISTER 3 MR3 (MR37–30)
(Address (SR4–SR0) = 12H)
Mode Register 3 is an 8-bit wide register.
Figure 34 shows the various operations under the control of
Mode Register 3. Bits MR36–MR30 are reserved and Logic “0”
should be written to them.
MODE REGISTER 3 (MR37–MR30) DESCRIPTION
DAC Switching Control (MR37)
This bit is used to switch the luminance signal onto the compos-
ite DAC. Figure 40 illustrates the DAC outputs and how they
switch when MR 37 is set to Logic “1”.
MR37
MR36
MR35
MR34
MR33
MR32
MR31
MR36-MR30
(RESERVED)
ZERO SHOULD BE
WRITTEN TO THESE BITS
MR37
0
1
DAC OUTPUT
SWITCHING
DAC A
DAC B
DAC C
COMPOSITE BLUE/COMP/U RED/CHROMA/V
GREEN/LUMA/Y BLUE/COMP/U RED/CHROMA/V
DAC D
GREEN/LUMA/Y
COMPOSITE
MR30
Figure 40. Mode Register 3
REV. A
–21–
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