ADV7175 View Datasheet(PDF) - Analog Devices
Part Name
Description
Manufacturer
ADV7175 Datasheet PDF : 36 Pages
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ADV7175/ADV7176
Mode 0 (CCIR-656): Slave Option.
(Timing Register 0 TR0 = X X X X X 0 0 0)
The ADV7175/ADV7176 is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel data.
All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before
and after each line during active picture and retrace. Mode 0 is illustrated in Figure 13. The HSYNC, FIELD/VSYNC and BLANK
(if not used) pins should be tied high in this mode.
ANALOG
VIDEO
INPUT PIXELS
NTSC SYSTEM
PAL SYSTEM
EAV CODE
C
r
C
b
Y
F
F
0
0
0X
0Y
8
0
1
0
8
0
1
0
4 PIXELS
4 PIXELS
END OF ACTIVE
VIDEO LINE
0F FAAA
0F FBBB
ANCILLARY DATA
(HANC)
268 PIXELS
280 PIXELS
SAV CODE
8
0
1
0
8
0
1
0
F
F
0
0
0
0
X
Y
CY
b
C
r
CY
b
C
r
CY
b
C
r
4 PIXELS
1440 PIXELS
4 PIXELS
1440 PIXELS
START OF ACTIVE
VIDEO LINE
Figure 13. Timing Mode 0 (Slave Mode)
Mode 0 (CCIR-656): Master Option.
(Timing Register 0 TR0 = X X X X X 0 0 1)
The ADV7175/ADV7176 generates H, V and F signals required for the SAV (start active video) and EAV (end active video) time
codes in the CCIR656 standard. The H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit is
output on the FIELD/VSYNC pin. Mode 0 is illustrated in Figure 14 (NTSC) and Figure 15 (PAL). The H, V and F transitions
relative to the video waveform are illustrated in Figure 16.
DISPLAY
VERTICAL BLANK
DISPLAY
522 523 524 525
1
H
V
2
3
4
5
6
7
F
EVEN FIELD ODD FIELD
8
9
10
11
DISPLAY
VERTICAL BLANK
20
21
22
DISPLAY
260 261 262 263 264 265 266 267 268 269 270 271 272 273 274
H
V
F
ODD FIELD EVEN FIELD
Figure 14. Timing Mode 0 (NTSC Master Mode)
REV. A
–9–
283 284 285
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